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arm64: dts: hi3660: add L2 cache topology 

This patch adds the L2 cache topology on 96boards Hikey960.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
This commit is contained in:
Leo Yan 2017-08-14 17:50:41 +08:00 committed by Wei Xu
parent 30fec8268c
commit a6d083441c
1 changed files with 16 additions and 0 deletions
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16
arch/arm64/boot/dts/hisilicon/hi3660.dtsi
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@ -58,6 +58,7 @@ cpu0: cpu@0 {
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
};
@ -66,6 +67,7 @@ cpu1: cpu@1 {
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
};
@ -74,6 +76,7 @@ cpu2: cpu@2 {
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
};
@ -82,6 +85,7 @@ cpu3: cpu@3 {
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
};
@ -90,6 +94,7 @@ cpu4: cpu@100 {
device_type = "cpu";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&A73_L2>;
cpu-idle-states = <
&CPU_NAP
&CPU_SLEEP
@ -102,6 +107,7 @@ cpu5: cpu@101 {
device_type = "cpu";
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&A73_L2>;
cpu-idle-states = <
&CPU_NAP
&CPU_SLEEP
@ -114,6 +120,7 @@ cpu6: cpu@102 {
device_type = "cpu";
reg = <0x0 0x102>;
enable-method = "psci";
next-level-cache = <&A73_L2>;
cpu-idle-states = <
&CPU_NAP
&CPU_SLEEP
@ -126,6 +133,7 @@ cpu7: cpu@103 {
device_type = "cpu";
reg = <0x0 0x103>;
enable-method = "psci";
next-level-cache = <&A73_L2>;
cpu-idle-states = <
&CPU_NAP
&CPU_SLEEP
@ -171,6 +179,14 @@ CLUSTER_SLEEP_1: cluster-sleep-1 {
min-residency-us = <20000>;
};
};
A53_L2: l2-cache0 {
compatible = "cache";
};
A73_L2: l2-cache1 {
compatible = "cache";
};
};
gic: interrupt-controller@e82b0000 {