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clk: mmp2: Add PLLs that are available on MMP3 

There are more PLLs on MMP3 and are configured slightly differently.
Tested on a MMP3-based Dell Wyse 3020 machine.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200309194254.29009-10-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Lubomir Rintel 2020-03-09 20:42:46 +01:00 committed by Stephen Boyd
parent 4d6da655d1
commit a70812b188
1 changed files with 27 additions and 7 deletions
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34
drivers/clk/mmp/clk-of-mmp2.c
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@ -57,10 +57,16 @@
#define APMU_USBHSIC0 0xf8
#define APMU_USBHSIC1 0xfc
#define MPMU_FCCR 0x8
#define MPMU_POSR 0x10
#define MPMU_UART_PLL 0x14
#define MPMU_PLL2_CR 0x34
#define MPMU_FCCR 0x8
#define MPMU_POSR 0x10
#define MPMU_UART_PLL 0x14
#define MPMU_PLL2_CR 0x34
/* MMP3 specific below */
#define MPMU_PLL3_CR 0x50
#define MPMU_PLL3_CTRL1 0x58
#define MPMU_PLL1_CTRL 0x5c
#define MPMU_PLL_DIFF_CTRL 0x68
#define MPMU_PLL2_CTRL1 0x414
enum mmp2_clk_model {
CLK_MODEL_MMP2,
@ -86,6 +92,14 @@ static struct mmp_param_pll_clk pll_clks[] = {
{MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10},
};
static struct mmp_param_pll_clk mmp3_pll_clks[] = {
{MMP2_CLK_PLL2, "pll1", 797330000, MPMU_FCCR, 0x4000, MPMU_POSR, 0, 26000000, MPMU_PLL1_CTRL, 25},
{MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10, 26000000, MPMU_PLL2_CTRL1, 25},
{MMP3_CLK_PLL1_P, "pll1_p", 0, MPMU_PLL_DIFF_CTRL, 0x0010, 0, 0, 797330000, MPMU_PLL_DIFF_CTRL, 0},
{MMP3_CLK_PLL2_P, "pll2_p", 0, MPMU_PLL_DIFF_CTRL, 0x0100, MPMU_PLL2_CR, 10, 26000000, MPMU_PLL_DIFF_CTRL, 5},
{MMP3_CLK_PLL3, "pll3", 0, MPMU_PLL3_CR, 0x0300, MPMU_PLL3_CR, 10, 26000000, MPMU_PLL3_CTRL1, 25},
};
static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
{MMP2_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
{MMP2_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
@ -127,9 +141,15 @@ static void mmp2_pll_init(struct mmp2_clk_unit *pxa_unit)
mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
ARRAY_SIZE(fixed_rate_clks));
mmp_register_pll_clks(unit, pll_clks,
pxa_unit->mpmu_base,
ARRAY_SIZE(pll_clks));
if (pxa_unit->model == CLK_MODEL_MMP3) {
mmp_register_pll_clks(unit, mmp3_pll_clks,
pxa_unit->mpmu_base,
ARRAY_SIZE(mmp3_pll_clks));
} else {
mmp_register_pll_clks(unit, pll_clks,
pxa_unit->mpmu_base,
ARRAY_SIZE(pll_clks));
}
mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
ARRAY_SIZE(fixed_factor_clks));