mirror of https://gitee.com/openkylin/linux.git
thermal: exynos: add ->tmu_clear_irqs method
Add ->tmu_clear_irqs method to struct exynos_tmu_data and use it instead exynos_tmu_clear_irqs(). Then add ->tmu_clear_irqs implementations for Exynos4210+ and Exynos5440. Finally remove no longer needed reg->tmu_int[stat,clear] abstractions and struct exynos_tmu_registers instances. There should be no functional changes caused by this patch. Cc: Amit Daniel Kachhap <amit.daniel@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Eduardo Valentin <edubezval@gmail.com> Cc: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
This commit is contained in:
Bartlomiej Zolnierkiewicz
Eduardo Valentin
parent
285d994a51
commit
a7331f72d3
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@ -56,6 +56,7 @@
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* @tmu_control: SoC specific TMU control method
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* @tmu_read: SoC specific TMU temperature read method
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* @tmu_set_emulation: SoC specific TMU emulation setting method
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* @tmu_clear_irqs: SoC specific TMU interrupts clearing method
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*/
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struct exynos_tmu_data {
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int id;
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@ -75,6 +76,7 @@ struct exynos_tmu_data {
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int (*tmu_read)(struct exynos_tmu_data *data);
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void (*tmu_set_emulation)(struct exynos_tmu_data *data,
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unsigned long temp);
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void (*tmu_clear_irqs)(struct exynos_tmu_data *data);
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};
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/*
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@ -131,23 +133,6 @@ static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
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return temp;
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}
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static void exynos_tmu_clear_irqs(struct exynos_tmu_data *data)
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{
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const struct exynos_tmu_registers *reg = data->pdata->registers;
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unsigned int val_irq;
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val_irq = readl(data->base + reg->tmu_intstat);
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/*
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* Clear the interrupts. Please note that the documentation for
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* Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly
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* states that INTCLEAR register has a different placing of bits
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* responsible for FALL IRQs than INTSTAT register. Exynos5420
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* and Exynos5440 documentation is correct (Exynos4210 doesn't
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* support FALL IRQs at all).
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*/
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writel(val_irq, data->base + reg->tmu_intclear);
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}
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static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info)
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{
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struct exynos_tmu_platform_data *pdata = data->pdata;
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@ -259,7 +244,7 @@ static int exynos4210_tmu_initialize(struct platform_device *pdev)
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writeb(pdata->trigger_levels[i], data->base +
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EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4);
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exynos_tmu_clear_irqs(data);
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data->tmu_clear_irqs(data);
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out:
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return ret;
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}
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@ -304,7 +289,7 @@ static int exynos4412_tmu_initialize(struct platform_device *pdev)
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writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
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writel(get_th_reg(data, 0, true), data->base + EXYNOS_THD_TEMP_FALL);
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exynos_tmu_clear_irqs(data);
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data->tmu_clear_irqs(data);
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/* if last threshold limit is also present */
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i = pdata->max_trigger_level - 1;
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@ -353,7 +338,7 @@ static int exynos5440_tmu_initialize(struct platform_device *pdev)
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writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH0);
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writel(0, data->base + EXYNOS5440_TMU_S0_7_TH1);
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exynos_tmu_clear_irqs(data);
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data->tmu_clear_irqs(data);
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/* if last threshold limit is also present */
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i = pdata->max_trigger_level - 1;
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@ -557,7 +542,7 @@ static void exynos_tmu_work(struct work_struct *work)
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clk_enable(data->clk);
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/* TODO: take action based on particular interrupt */
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exynos_tmu_clear_irqs(data);
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data->tmu_clear_irqs(data);
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clk_disable(data->clk);
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mutex_unlock(&data->lock);
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@ -565,6 +550,40 @@ static void exynos_tmu_work(struct work_struct *work)
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enable_irq(data->irq);
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}
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static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data)
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{
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unsigned int val_irq;
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u32 tmu_intstat, tmu_intclear;
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if (data->soc == SOC_ARCH_EXYNOS5260) {
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tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT;
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tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR;
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} else {
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tmu_intstat = EXYNOS_TMU_REG_INTSTAT;
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tmu_intclear = EXYNOS_TMU_REG_INTCLEAR;
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}
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val_irq = readl(data->base + tmu_intstat);
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/*
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* Clear the interrupts. Please note that the documentation for
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* Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly
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* states that INTCLEAR register has a different placing of bits
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* responsible for FALL IRQs than INTSTAT register. Exynos5420
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* and Exynos5440 documentation is correct (Exynos4210 doesn't
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* support FALL IRQs at all).
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*/
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writel(val_irq, data->base + tmu_intclear);
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}
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static void exynos5440_tmu_clear_irqs(struct exynos_tmu_data *data)
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{
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unsigned int val_irq;
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val_irq = readl(data->base + EXYNOS5440_TMU_S0_7_IRQ);
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/* clear the interrupts */
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writel(val_irq, data->base + EXYNOS5440_TMU_S0_7_IRQ);
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}
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static irqreturn_t exynos_tmu_irq(int irq, void *id)
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{
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struct exynos_tmu_data *data = id;
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@ -760,6 +779,7 @@ static int exynos_tmu_probe(struct platform_device *pdev)
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data->tmu_initialize = exynos4210_tmu_initialize;
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data->tmu_control = exynos4210_tmu_control;
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data->tmu_read = exynos4210_tmu_read;
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data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
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break;
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case SOC_ARCH_EXYNOS3250:
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case SOC_ARCH_EXYNOS4412:
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@ -771,12 +791,14 @@ static int exynos_tmu_probe(struct platform_device *pdev)
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data->tmu_control = exynos4210_tmu_control;
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data->tmu_read = exynos4412_tmu_read;
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data->tmu_set_emulation = exynos4412_tmu_set_emulation;
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data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
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break;
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case SOC_ARCH_EXYNOS5440:
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data->tmu_initialize = exynos5440_tmu_initialize;
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data->tmu_control = exynos5440_tmu_control;
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data->tmu_read = exynos5440_tmu_read;
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data->tmu_set_emulation = exynos5440_tmu_set_emulation;
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data->tmu_clear_irqs = exynos5440_tmu_clear_irqs;
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break;
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default:
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ret = -EINVAL;
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@ -67,17 +67,6 @@ enum soc_type {
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#define TMU_SUPPORTS(a, b) (a->features & TMU_SUPPORT_ ## b)
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/**
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* struct exynos_tmu_register - register descriptors to access registers.
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* The register validity may vary slightly across different exynos SOC's.
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* @tmu_intstat: Register containing the interrupt status values.
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* @tmu_intclear: Register for clearing the raised interrupt status.
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*/
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struct exynos_tmu_registers {
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u32 tmu_intstat;
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u32 tmu_intclear;
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};
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/**
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* struct exynos_tmu_platform_data
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* @threshold: basic temperature for generating interrupt
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@ -127,8 +116,6 @@ struct exynos_tmu_registers {
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* @freq_clip_table: Table representing frequency reduction percentage.
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* @freq_tab_count: Count of the above table as frequency reduction may
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* applicable to only some of the trigger levels.
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* @registers: Pointer to structure containing all the TMU controller registers
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* and bitfields shifts and masks.
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* @features: a bitfield value indicating the features supported in SOC like
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* emulation, multi instance etc
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*
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@ -158,7 +145,6 @@ struct exynos_tmu_platform_data {
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enum soc_type type;
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struct freq_clip_table freq_tab[4];
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unsigned int freq_tab_count;
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const struct exynos_tmu_registers *registers;
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unsigned int features;
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};
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@ -25,11 +25,6 @@
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#include "exynos_tmu_data.h"
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#if defined(CONFIG_CPU_EXYNOS4210)
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static const struct exynos_tmu_registers exynos4210_tmu_registers = {
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.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
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.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
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};
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struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
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.tmu_data = {
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{
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@ -64,7 +59,6 @@ struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
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},
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.freq_tab_count = 2,
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.type = SOC_ARCH_EXYNOS4210,
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.registers = &exynos4210_tmu_registers,
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},
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},
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.tmu_count = 1,
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@ -72,11 +66,6 @@ struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
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#endif
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#if defined(CONFIG_SOC_EXYNOS3250)
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static const struct exynos_tmu_registers exynos3250_tmu_registers = {
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.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
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.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
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};
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#define EXYNOS3250_TMU_DATA \
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.threshold_falling = 10, \
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.trigger_levels[0] = 70, \
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@ -112,7 +101,6 @@ static const struct exynos_tmu_registers exynos3250_tmu_registers = {
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.temp_level = 95, \
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}, \
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.freq_tab_count = 2, \
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.registers = &exynos3250_tmu_registers, \
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.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
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TMU_SUPPORT_EMUL_TIME)
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#endif
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@ -131,11 +119,6 @@ struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
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#endif
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#if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
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static const struct exynos_tmu_registers exynos4412_tmu_registers = {
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.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
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.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
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};
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#define EXYNOS4412_TMU_DATA \
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.threshold_falling = 10, \
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.trigger_levels[0] = 70, \
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@ -171,7 +154,6 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
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.temp_level = 95, \
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}, \
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.freq_tab_count = 2, \
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.registers = &exynos4412_tmu_registers, \
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.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
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TMU_SUPPORT_EMUL_TIME)
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#endif
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@ -202,11 +184,6 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
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#endif
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#if defined(CONFIG_SOC_EXYNOS5260)
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static const struct exynos_tmu_registers exynos5260_tmu_registers = {
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.tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT,
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.tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR,
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};
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#define __EXYNOS5260_TMU_DATA \
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.threshold_falling = 10, \
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.trigger_levels[0] = 85, \
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@ -242,7 +219,6 @@ static const struct exynos_tmu_registers exynos5260_tmu_registers = {
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.temp_level = 103, \
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}, \
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.freq_tab_count = 2, \
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.registers = &exynos5260_tmu_registers, \
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#define EXYNOS5260_TMU_DATA \
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__EXYNOS5260_TMU_DATA \
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@ -263,11 +239,6 @@ struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
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#endif
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#if defined(CONFIG_SOC_EXYNOS5420)
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static const struct exynos_tmu_registers exynos5420_tmu_registers = {
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.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
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.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
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};
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#define __EXYNOS5420_TMU_DATA \
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.threshold_falling = 10, \
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.trigger_levels[0] = 85, \
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@ -303,7 +274,6 @@ static const struct exynos_tmu_registers exynos5420_tmu_registers = {
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.temp_level = 103, \
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}, \
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.freq_tab_count = 2, \
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.registers = &exynos5420_tmu_registers, \
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#define EXYNOS5420_TMU_DATA \
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__EXYNOS5420_TMU_DATA \
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@ -330,11 +300,6 @@ struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
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#endif
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#if defined(CONFIG_SOC_EXYNOS5440)
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static const struct exynos_tmu_registers exynos5440_tmu_registers = {
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.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
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.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
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};
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#define EXYNOS5440_TMU_DATA \
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.trigger_levels[0] = 100, \
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.trigger_levels[4] = 105, \
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@ -354,7 +319,6 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
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.second_point_trim = 70, \
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.default_temp_offset = 25, \
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.type = SOC_ARCH_EXYNOS5440, \
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.registers = &exynos5440_tmu_registers, \
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.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
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TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
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