mirror of https://gitee.com/openkylin/linux.git
drm/i915/cml: Add CML PCI IDS
Comet Lake is a Intel Processor containing Gen9 Intel HD Graphics. This patch adds the initial set of PCI IDs. Comet Lake comes off of Coffee Lake - adding the IDs to Coffee Lake ID list. More support and features will be in the patches that follow. v2: Split IDs according to GT. (Rodrigo) v3: Update IDs. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190318200133.9666-1-anusha.srivatsa@intel.com
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@ -795,6 +795,8 @@ static const struct pci_device_id pciidlist[] = {
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INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
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INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
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INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
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INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info),
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INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
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INTEL_CNL_IDS(&intel_cannonlake_info),
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INTEL_ICL_11_IDS(&intel_icelake_11_info),
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{0, 0, 0}
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@ -373,6 +373,30 @@
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#define INTEL_AML_CFL_GT2_IDS(info) \
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INTEL_VGA_DEVICE(0x87CA, info)
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/* CML GT1 */
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#define INTEL_CML_GT1_IDS(info) \
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INTEL_VGA_DEVICE(0x9B21, info), \
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INTEL_VGA_DEVICE(0x9BAA, info), \
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INTEL_VGA_DEVICE(0x9BAB, info), \
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INTEL_VGA_DEVICE(0x9BAC, info), \
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INTEL_VGA_DEVICE(0x9BA0, info), \
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INTEL_VGA_DEVICE(0x9BA5, info), \
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INTEL_VGA_DEVICE(0x9BA8, info), \
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INTEL_VGA_DEVICE(0x9BA4, info), \
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INTEL_VGA_DEVICE(0x9BA2, info)
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/* CML GT2 */
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#define INTEL_CML_GT2_IDS(info) \
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INTEL_VGA_DEVICE(0x9B41, info), \
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INTEL_VGA_DEVICE(0x9BCA, info), \
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INTEL_VGA_DEVICE(0x9BCB, info), \
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INTEL_VGA_DEVICE(0x9BCC, info), \
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INTEL_VGA_DEVICE(0x9BC0, info), \
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INTEL_VGA_DEVICE(0x9BC5, info), \
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INTEL_VGA_DEVICE(0x9BC8, info), \
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INTEL_VGA_DEVICE(0x9BC4, info), \
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INTEL_VGA_DEVICE(0x9BC2, info)
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#define INTEL_KBL_IDS(info) \
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INTEL_KBL_GT1_IDS(info), \
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INTEL_KBL_GT2_IDS(info), \
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@ -436,7 +460,9 @@
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INTEL_WHL_U_GT1_IDS(info), \
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INTEL_WHL_U_GT2_IDS(info), \
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INTEL_WHL_U_GT3_IDS(info), \
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INTEL_AML_CFL_GT2_IDS(info)
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INTEL_AML_CFL_GT2_IDS(info), \
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INTEL_CML_GT1_IDS(info), \
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INTEL_CML_GT2_IDS(info)
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/* CNL */
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#define INTEL_CNL_IDS(info) \
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