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Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6 

* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: (26 commits)
  sh: remove dead config symbols from SH code
  sh: Kill off broken snapgear ds1302 code.
  sh: Add a dummy vga.h.
  rtc: rtc-sh: Zero out tm value for invalid rtc states.
  rtc: sh-rtc: Handle rtc_device_register() failure properly.
  sh: Fix heartbeart on Solution Engine series
  sh: Remove SCI_NPORTS from sh-sci.h
  sh: Fix up PAGE_KERNEL_PCC() for nommu.
  sh: hs7751rvoip: Kill off dead IPR IRQ mappings.
  sh: hs7751rvoip: irq.c needs linux/interrupt.h.
  sh: Kill off __{copy,clear}_user_page().
  sh: Optimized copy_{to,from}_user_page() for SH-4.
  sh: Wire up clear_user_highpage().
  sh: Kill off the remaining ST40 cruft.
  superhyway: Handle device_register() retval properly.
  sh: kgdb sysrq depends on magic sysrq.
  sh: Add -Werror for clean directories.
  sh: Fix up kgdb build with modular sh-sci.
  sh: Export __{s,u}divsi3_i4i on all CPUs.
  sh: Fix up kgdb-on-NMI branch target.
  ...
This commit is contained in:
Linus Torvalds 2007-11-09 15:25:29 -08:00
parent 45ff993d2b 06e5fda184
commit a80b824f0b
45 changed files with 148 additions and 1194 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/sh/Kconfig
View File

@ -211,10 +211,12 @@ config SH_SOLUTION_ENGINE
bool "SolutionEngine"
select SOLUTION_ENGINE
select CPU_HAS_IPR_IRQ
depends on CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7750
depends on CPU_SUBTYPE_SH7705 || CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7710 || \
CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \
CPU_SUBTYPE_SH7750R
help
Select SolutionEngine if configuring for a Hitachi SH7709
or SH7750 evaluation board.
Select SolutionEngine if configuring for a Hitachi SH7705, SH7709,
SH7710, SH7712, SH7750, SH7750S or SH7750R evaluation board.
config SH_7206_SOLUTION_ENGINE
bool "SolutionEngine7206"
@ -603,7 +605,7 @@ config BOOT_LINK_OFFSET
config UBC_WAKEUP
bool "Wakeup UBC on startup"
depends on CPU_SH4
depends on CPU_SH4 && !CPU_SH4A
help
Selecting this option will wakeup the User Break Controller (UBC) on
startup. Although the UBC is left in an awake state when the processor

3
arch/sh/Kconfig.debug
View File

@ -124,12 +124,13 @@ config KGDB_NMI
config SH_KGDB_CONSOLE
bool "Console messages through GDB"
depends on !SERIAL_SH_SCI_CONSOLE
depends on !SERIAL_SH_SCI_CONSOLE && SERIAL_SH_SCI=y
select SERIAL_CORE_CONSOLE
default n
config KGDB_SYSRQ
bool "Allow SysRq 'G' to enter KGDB"
depends on MAGIC_SYSRQ
default y
comment "Serial port setup"

1
arch/sh/boards/renesas/hs7751rvoip/irq.c
View File

@ -12,6 +12,7 @@
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/hs7751rvoip.h>

19
arch/sh/boards/renesas/hs7751rvoip/setup.c
View File

@ -15,20 +15,6 @@
#include <asm/io.h>
#include <asm/machvec.h>
static struct ipr_data hs77501rvoip_ipr_map[] = {
#if defined(CONFIG_HS7751RVOIP_CODEC)
{ DMTE0_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
{ DMTE1_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
#endif
};
static void __init hs7751rvoip_init_irq(void)
{
make_ipr_irq(hs77501rvoip_ipr_map, ARRAY_SIZE(hs77501rvoip_ipr_map));
init_hs7751rvoip_IRQ();
}
static void hs7751rvoip_power_off(void)
{
ctrl_outw(ctrl_inw(PA_OUTPORTR) & 0xffdf, PA_OUTPORTR);
@ -75,14 +61,13 @@ static int __init hs7751rvoip_cf_init(void)
return 0;
}
device_initcall(hs7751rvoip_cf_init);
/*
* Initialize the board
*/
static void __init hs7751rvoip_setup(char **cmdline_p)
{
device_initcall(hs7751rvoip_cf_init);
ctrl_outb(0xf0, PA_OUTPORTR);
pm_power_off = hs7751rvoip_power_off;
@ -115,6 +100,6 @@ static struct sh_machine_vector mv_hs7751rvoip __initmv = {
.mv_outsw = hs7751rvoip_outsw,
.mv_outsl = hs7751rvoip_outsl,
.mv_init_irq = hs7751rvoip_init_irq,
.mv_init_irq = init_hs7751rvoip_IRQ,
.mv_ioport_map = hs7751rvoip_ioport_map,
};

1
arch/sh/boards/renesas/sh7710voipgw/setup.c
View File

@ -11,7 +11,6 @@
#include <asm/machvec.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/irq.h>
static struct ipr_data sh7710voipgw_ipr_map[] = {
{ TIMER2_IRQ, TIMER2_IPR_ADDR, TIMER2_IPR_POS, TIMER2_PRIORITY },

1
arch/sh/boards/se/7206/irq.c
View File

@ -9,7 +9,6 @@
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <asm/se7206.h>

1
arch/sh/boards/se/770x/setup.c
View File

@ -94,6 +94,7 @@ static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
static struct heartbeat_data heartbeat_data = {
.bit_pos = heartbeat_bit_pos,
.nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
.regsize = 16,
};
static struct resource heartbeat_resources[] = {

8
arch/sh/boards/se/7722/setup.c
View File

@ -16,8 +16,13 @@
#include <asm/machvec.h>
#include <asm/se7722.h>
#include <asm/io.h>
#include <asm/heartbeat.h>
/* Heartbeat */
static struct heartbeat_data heartbeat_data = {
.regsize = 16,
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
@ -29,6 +34,9 @@ static struct resource heartbeat_resources[] = {
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
};

8
arch/sh/boards/se/7780/setup.c
View File

@ -14,8 +14,13 @@
#include <asm/machvec.h>
#include <asm/se7780.h>
#include <asm/io.h>
#include <asm/heartbeat.h>
/* Heartbeat */
static struct heartbeat_data heartbeat_data = {
.regsize = 16,
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
@ -27,6 +32,9 @@ static struct resource heartbeat_resources[] = {
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
};

3
arch/sh/boards/snapgear/Makefile
View File

@ -2,5 +2,4 @@
# Makefile for the SnapGear specific parts of the kernel
#
obj-y := setup.o io.o rtc.o
obj-y := setup.o io.o

309
arch/sh/boards/snapgear/rtc.c
View File

@ -1,309 +0,0 @@
/****************************************************************************/
/*
* linux/arch/sh/boards/snapgear/rtc.c -- Secureedge5410 RTC code
*
* Copyright (C) 2002 David McCullough <davidm@snapgear.com>
* Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org>
*
* The SecureEdge5410 can have one of 2 real time clocks, the SH
* built in version or the preferred external DS1302. Here we work out
* each to see what we have and then run with it.
*/
/****************************************************************************/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/time.h>
#include <linux/rtc.h>
#include <linux/mc146818rtc.h>
#include <asm/io.h>
static int use_ds1302;
/****************************************************************************/
/*
* we need to implement a DS1302 driver here that can operate in
* conjunction with the builtin rtc driver which is already quite friendly
*/
/*****************************************************************************/
#define RTC_CMD_READ 0x81 /* Read command */
#define RTC_CMD_WRITE 0x80 /* Write command */
#define RTC_ADDR_YEAR 0x06 /* Address of year register */
#define RTC_ADDR_DAY 0x05 /* Address of day of week register */
#define RTC_ADDR_MON 0x04 /* Address of month register */
#define RTC_ADDR_DATE 0x03 /* Address of day of month register */
#define RTC_ADDR_HOUR 0x02 /* Address of hour register */
#define RTC_ADDR_MIN 0x01 /* Address of minute register */
#define RTC_ADDR_SEC 0x00 /* Address of second register */
#define RTC_RESET 0x1000
#define RTC_IODATA 0x0800
#define RTC_SCLK 0x0400
#define set_dirp(x)
#define get_dirp(x) 0
#define set_dp(x) SECUREEDGE_WRITE_IOPORT(x, 0x1c00)
#define get_dp(x) SECUREEDGE_READ_IOPORT()
static void ds1302_sendbits(unsigned int val)
{
int i;
for (i = 8; (i); i--, val >>= 1) {
set_dp((get_dp() & ~RTC_IODATA) | ((val & 0x1) ? RTC_IODATA : 0));
set_dp(get_dp() | RTC_SCLK); // clock high
set_dp(get_dp() & ~RTC_SCLK); // clock low
}
}
static unsigned int ds1302_recvbits(void)
{
unsigned int val;
int i;
for (i = 0, val = 0; (i < 8); i++) {
val |= (((get_dp() & RTC_IODATA) ? 1 : 0) << i);
set_dp(get_dp() | RTC_SCLK); // clock high
set_dp(get_dp() & ~RTC_SCLK); // clock low
}
return(val);
}
static unsigned int ds1302_readbyte(unsigned int addr)
{
unsigned int val;
unsigned long flags;
local_irq_save(flags);
set_dirp(get_dirp() | RTC_RESET | RTC_IODATA | RTC_SCLK);
set_dp(get_dp() & ~(RTC_RESET | RTC_IODATA | RTC_SCLK));
set_dp(get_dp() | RTC_RESET);
ds1302_sendbits(((addr & 0x3f) << 1) | RTC_CMD_READ);
set_dirp(get_dirp() & ~RTC_IODATA);
val = ds1302_recvbits();
set_dp(get_dp() & ~RTC_RESET);
local_irq_restore(flags);
return(val);
}
static void ds1302_writebyte(unsigned int addr, unsigned int val)
{
unsigned long flags;
local_irq_save(flags);
set_dirp(get_dirp() | RTC_RESET | RTC_IODATA | RTC_SCLK);
set_dp(get_dp() & ~(RTC_RESET | RTC_IODATA | RTC_SCLK));
set_dp(get_dp() | RTC_RESET);
ds1302_sendbits(((addr & 0x3f) << 1) | RTC_CMD_WRITE);
ds1302_sendbits(val);
set_dp(get_dp() & ~RTC_RESET);
local_irq_restore(flags);
}
static void ds1302_reset(void)
{
unsigned long flags;
/* Hardware dependent reset/init */
local_irq_save(flags);
set_dirp(get_dirp() | RTC_RESET | RTC_IODATA | RTC_SCLK);
set_dp(get_dp() & ~(RTC_RESET | RTC_IODATA | RTC_SCLK));
local_irq_restore(flags);
}
/*****************************************************************************/
static inline int bcd2int(int val)
{
return((((val & 0xf0) >> 4) * 10) + (val & 0xf));
}
static inline int int2bcd(int val)
{
return(((val / 10) << 4) + (val % 10));
}
/*****************************************************************************/
/*
* Write and Read some RAM in the DS1302, if it works assume it's there
* Otherwise use the SH4 internal RTC
*/
void snapgear_rtc_gettimeofday(struct timespec *);
int snapgear_rtc_settimeofday(const time_t);
void __init secureedge5410_rtc_init(void)
{
unsigned char *test = "snapgear";
int i;
ds1302_reset();
use_ds1302 = 1;
for (i = 0; test[i]; i++)
ds1302_writebyte(32 + i, test[i]);
for (i = 0; test[i]; i++)
if (ds1302_readbyte(32 + i) != test[i]) {
use_ds1302 = 0;
break;
}
if (use_ds1302) {
rtc_sh_get_time = snapgear_rtc_gettimeofday;
rtc_sh_set_time = snapgear_rtc_settimeofday;
}
printk("SnapGear RTC: using %s rtc.\n", use_ds1302 ? "ds1302" : "internal");
}
/****************************************************************************/
/*
* our generic interface that chooses the correct code to use
*/
void snapgear_rtc_gettimeofday(struct timespec *ts)
{
unsigned int sec, min, hr, day, mon, yr;
if (!use_ds1302)
return;
sec = bcd2int(ds1302_readbyte(RTC_ADDR_SEC));
min = bcd2int(ds1302_readbyte(RTC_ADDR_MIN));
hr = bcd2int(ds1302_readbyte(RTC_ADDR_HOUR));
day = bcd2int(ds1302_readbyte(RTC_ADDR_DATE));
mon = bcd2int(ds1302_readbyte(RTC_ADDR_MON));
yr = bcd2int(ds1302_readbyte(RTC_ADDR_YEAR));
bad_time:
if (yr > 99 || mon < 1 || mon > 12 || day > 31 || day < 1 ||
hr > 23 || min > 59 || sec > 59) {
printk(KERN_ERR
"SnapGear RTC: invalid value, resetting to 1 Jan 2000\n");
ds1302_writebyte(RTC_ADDR_MIN, min = 0);
ds1302_writebyte(RTC_ADDR_HOUR, hr = 0);
ds1302_writebyte(RTC_ADDR_DAY, 7);
ds1302_writebyte(RTC_ADDR_DATE, day = 1);
ds1302_writebyte(RTC_ADDR_MON, mon = 1);
ds1302_writebyte(RTC_ADDR_YEAR, yr = 0);
ds1302_writebyte(RTC_ADDR_SEC, sec = 0);
}
ts->tv_sec = mktime(2000 + yr, mon, day, hr, min, sec);
if (ts->tv_sec < 0) {
#if 0
printk("BAD TIME %d %d %d %d %d %d\n", yr, mon, day, hr, min, sec);
#endif
yr = 100;
goto bad_time;
}
ts->tv_nsec = 0;
}
int snapgear_rtc_settimeofday(const time_t secs)
{
int retval = 0;
int real_seconds, real_minutes, cmos_minutes;
unsigned long nowtime;
if (!use_ds1302)
return 0;
/*
* This is called direct from the kernel timer handling code.
* It is supposed to synchronize the kernel clock to the RTC.
*/
nowtime = secs;
/* STOP RTC */
ds1302_writebyte(RTC_ADDR_SEC, ds1302_readbyte(RTC_ADDR_SEC) | 0x80);
cmos_minutes = bcd2int(ds1302_readbyte(RTC_ADDR_MIN));
/*
* since we're only adjusting minutes and seconds,
* don't interfere with hour overflow. This avoids
* messing with unknown time zones but requires your
* RTC not to be off by more than 15 minutes
*/
real_seconds = nowtime % 60;
real_minutes = nowtime / 60;
if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
real_minutes += 30; /* correct for half hour time zone */
real_minutes %= 60;
if (abs(real_minutes - cmos_minutes) < 30) {
ds1302_writebyte(RTC_ADDR_MIN, int2bcd(real_minutes));
ds1302_writebyte(RTC_ADDR_SEC, int2bcd(real_seconds));
} else {
printk(KERN_WARNING
"SnapGear RTC: can't update from %d to %d\n",
cmos_minutes, real_minutes);
retval = -1;
}
/* START RTC */
ds1302_writebyte(RTC_ADDR_SEC, ds1302_readbyte(RTC_ADDR_SEC) & ~0x80);
return(0);
}
unsigned char secureedge5410_cmos_read(int addr)
{
unsigned char val = 0;
if (!use_ds1302)
return(__CMOS_READ(addr, w));
switch(addr) {
case RTC_SECONDS: val = ds1302_readbyte(RTC_ADDR_SEC); break;
case RTC_SECONDS_ALARM: break;
case RTC_MINUTES: val = ds1302_readbyte(RTC_ADDR_MIN); break;
case RTC_MINUTES_ALARM: break;
case RTC_HOURS: val = ds1302_readbyte(RTC_ADDR_HOUR); break;
case RTC_HOURS_ALARM: break;
case RTC_DAY_OF_WEEK: val = ds1302_readbyte(RTC_ADDR_DAY); break;
case RTC_DAY_OF_MONTH: val = ds1302_readbyte(RTC_ADDR_DATE); break;
case RTC_MONTH: val = ds1302_readbyte(RTC_ADDR_MON); break;
case RTC_YEAR: val = ds1302_readbyte(RTC_ADDR_YEAR); break;
case RTC_REG_A: /* RTC_FREQ_SELECT */ break;
case RTC_REG_B: /* RTC_CONTROL */ break;
case RTC_REG_C: /* RTC_INTR_FLAGS */ break;
case RTC_REG_D: val = RTC_VRT /* RTC_VALID */; break;
default: break;
}
return(val);
}
void secureedge5410_cmos_write(unsigned char val, int addr)
{
if (!use_ds1302) {
__CMOS_WRITE(val, addr, w);
return;
}
switch(addr) {
case RTC_SECONDS: ds1302_writebyte(RTC_ADDR_SEC, val); break;
case RTC_SECONDS_ALARM: break;
case RTC_MINUTES: ds1302_writebyte(RTC_ADDR_MIN, val); break;
case RTC_MINUTES_ALARM: break;
case RTC_HOURS: ds1302_writebyte(RTC_ADDR_HOUR, val); break;
case RTC_HOURS_ALARM: break;
case RTC_DAY_OF_WEEK: ds1302_writebyte(RTC_ADDR_DAY, val); break;
case RTC_DAY_OF_MONTH: ds1302_writebyte(RTC_ADDR_DATE, val); break;
case RTC_MONTH: ds1302_writebyte(RTC_ADDR_MON, val); break;
case RTC_YEAR: ds1302_writebyte(RTC_ADDR_YEAR, val); break;
case RTC_REG_A: /* RTC_FREQ_SELECT */ break;
case RTC_REG_B: /* RTC_CONTROL */ break;
case RTC_REG_C: /* RTC_INTR_FLAGS */ break;
case RTC_REG_D: /* RTC_VALID */ break;
default: break;
}
}

16
arch/sh/boards/snapgear/setup.c
View File

@ -22,20 +22,15 @@
#include <asm/snapgear.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/rtc.h>
#include <asm/cpu/timer.h>
extern void secureedge5410_rtc_init(void);
extern void pcibios_init(void);
/****************************************************************************/
/*
* EraseConfig handling functions
*/
static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id)
{
volatile char dummy __attribute__((unused)) = * (volatile char *) 0xb8000000;
(void)ctrl_inb(0xb8000000); /* dummy read */
printk("SnapGear: erase switch interrupt!\n");
@ -75,20 +70,11 @@ static void __init init_snapgear_IRQ(void)
plat_irq_setup_pins(IRQ_MODE_IRQ);
}
/*
* Initialize the board
*/
static void __init snapgear_setup(char **cmdline_p)
{
board_time_init = secureedge5410_rtc_init;
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_snapgear __initmv = {
.mv_name = "SnapGear SecureEdge5410",
.mv_setup = snapgear_setup,
.mv_nr_irqs = 72,
.mv_inb = snapgear_inb,

2
arch/sh/boot/Makefile
View File

@ -39,7 +39,7 @@ KERNEL_LOAD := $(shell /bin/bash -c 'printf "0x%8x" \
quiet_cmd_uimage = UIMAGE $@
cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A sh -O linux -T kernel \
-C gzip -a $(KERNEL_LOAD) -e $(KERNEL_LOAD) \
-C none -a $(KERNEL_LOAD) -e $(KERNEL_LOAD) \
-n 'Linux-$(KERNELRELEASE)' -d $< $@
$(obj)/uImage: $(obj)/zImage FORCE

2
arch/sh/cchips/hd6446x/Makefile
View File

@ -1,2 +1,4 @@
obj-$(CONFIG_HD64461) += hd64461.o
obj-$(CONFIG_HD64465) += hd64465/
EXTRA_CFLAGS += -Werror

1
arch/sh/cchips/voyagergx/Makefile
View File

@ -6,3 +6,4 @@ obj-y := irq.o setup.o
obj-$(CONFIG_USB_OHCI_HCD) += consistent.o
EXTRA_CFLAGS += -Werror

1
arch/sh/drivers/pci/Makefile
View File

@ -5,7 +5,6 @@
obj-y += pci.o
obj-$(CONFIG_PCI_AUTO) += pci-auto.o
obj-$(CONFIG_CPU_SUBTYPE_ST40STB1) += pci-st40.o
obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o
obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o
obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o

488
arch/sh/drivers/pci/pci-st40.c
View File

@ -1,488 +0,0 @@
/*
* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Support functions for the ST40 PCI hardware.
*/
#include <linux/kernel.h>
#include <linux/smp.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <asm/pci.h>
#include <linux/irq.h>
#include <linux/interrupt.h> /* irqreturn_t */
#include "pci-st40.h"
/* This is in P2 of course */
#define ST40PCI_BASE_ADDRESS (0xb0000000)
#define ST40PCI_MEM_ADDRESS (ST40PCI_BASE_ADDRESS+0x0)
#define ST40PCI_IO_ADDRESS (ST40PCI_BASE_ADDRESS+0x06000000)
#define ST40PCI_REG_ADDRESS (ST40PCI_BASE_ADDRESS+0x07000000)
#define ST40PCI_REG(x) (ST40PCI_REG_ADDRESS+(ST40PCI_##x))
#define ST40PCI_REG_INDEXED(reg, index) \
(ST40PCI_REG(reg##0) + \
((ST40PCI_REG(reg##1) - ST40PCI_REG(reg##0))*index))
#define ST40PCI_WRITE(reg,val) writel((val),ST40PCI_REG(reg))
#define ST40PCI_WRITE_SHORT(reg,val) writew((val),ST40PCI_REG(reg))
#define ST40PCI_WRITE_BYTE(reg,val) writeb((val),ST40PCI_REG(reg))
#define ST40PCI_WRITE_INDEXED(reg, index, val) \
writel((val), ST40PCI_REG_INDEXED(reg, index));
#define ST40PCI_READ(reg) readl(ST40PCI_REG(reg))
#define ST40PCI_READ_SHORT(reg) readw(ST40PCI_REG(reg))
#define ST40PCI_READ_BYTE(reg) readb(ST40PCI_REG(reg))
#define ST40PCI_SERR_IRQ 64
#define ST40PCI_ERR_IRQ 65
/* Macros to extract PLL params */
#define PLL_MDIV(reg) ( ((unsigned)reg) & 0xff )
#define PLL_NDIV(reg) ( (((unsigned)reg)>>8) & 0xff )
#define PLL_PDIV(reg) ( (((unsigned)reg)>>16) & 0x3 )
#define PLL_SETUP(reg) ( (((unsigned)reg)>>19) & 0x1ff )
/* Build up the appropriate settings */
#define PLL_SET(mdiv,ndiv,pdiv,setup) \
( ((mdiv)&0xff) | (((ndiv)&0xff)<<8) | (((pdiv)&3)<<16)| (((setup)&0x1ff)<<19))
#define PLLPCICR (0xbb040000+0x10)
#define PLLPCICR_POWERON (1<<28)
#define PLLPCICR_OUT_EN (1<<29)
#define PLLPCICR_LOCKSELECT (1<<30)
#define PLLPCICR_LOCK (1<<31)
#define PLL_25MHZ 0x793c8512
#define PLL_33MHZ PLL_SET(18,88,3,295)
static void pci_set_rbar_region(unsigned int region, unsigned long localAddr,
unsigned long pciOffset, unsigned long regionSize);
static __init void SetPCIPLL(void)
{
{
/* Lets play with the PLL values */
unsigned long pll1cr1;
unsigned long mdiv, ndiv, pdiv;
unsigned long muxcr;
unsigned int muxcr_ratios[4] = { 8, 16, 21, 1 };
unsigned int freq;
#define CLKGENA 0xbb040000
#define CLKGENA_PLL2_MUXCR CLKGENA + 0x48
pll1cr1 = ctrl_inl(PLLPCICR);
printk("PLL1CR1 %08lx\n", pll1cr1);
mdiv = PLL_MDIV(pll1cr1);
ndiv = PLL_NDIV(pll1cr1);
pdiv = PLL_PDIV(pll1cr1);
printk("mdiv %02lx ndiv %02lx pdiv %02lx\n", mdiv, ndiv, pdiv);
freq = ((2*27*ndiv)/mdiv) / (1 << pdiv);
printk("PLL freq %dMHz\n", freq);
muxcr = ctrl_inl(CLKGENA_PLL2_MUXCR);
printk("PCI freq %dMhz\n", freq / muxcr_ratios[muxcr & 3]);
}
}
struct pci_err {
unsigned mask;
const char *error_string;
};
static struct pci_err int_error[]={
{ INT_MNLTDIM,"MNLTDIM: Master non-lock transfer"},
{ INT_TTADI, "TTADI: Illegal byte enable in I/O transfer"},
{ INT_TMTO, "TMTO: Target memory read/write timeout"},
{ INT_MDEI, "MDEI: Master function disable error"},
{ INT_APEDI, "APEDI: Address parity error"},
{ INT_SDI, "SDI: SERR detected"},
{ INT_DPEITW, "DPEITW: Data parity error target write"},
{ INT_PEDITR, "PEDITR: PERR detected"},
{ INT_TADIM, "TADIM: Target abort detected"},
{ INT_MADIM, "MADIM: Master abort detected"},
{ INT_MWPDI, "MWPDI: PERR from target at data write"},
{ INT_MRDPEI, "MRDPEI: Master read data parity error"}
};
#define NUM_PCI_INT_ERRS ARRAY_SIZE(int_error)
static struct pci_err aint_error[]={
{ AINT_MBI, "MBI: Master broken"},
{ AINT_TBTOI, "TBTOI: Target bus timeout"},
{ AINT_MBTOI, "MBTOI: Master bus timeout"},
{ AINT_TAI, "TAI: Target abort"},
{ AINT_MAI, "MAI: Master abort"},
{ AINT_RDPEI, "RDPEI: Read data parity"},
{ AINT_WDPE, "WDPE: Write data parity"}
};
#define NUM_PCI_AINT_ERRS ARRAY_SIZE(aint_error)
static void print_pci_errors(unsigned reg,struct pci_err *error,int num_errors)
{
int i;
for(i=0;i<num_errors;i++) {
if(reg & error[i].mask) {
printk("%s\n",error[i].error_string);
}
}
}
static char * pci_commands[16]={
"Int Ack",
"Special Cycle",
"I/O Read",
"I/O Write",
"Reserved",
"Reserved",
"Memory Read",
"Memory Write",
"Reserved",
"Reserved",
"Configuration Read",
"Configuration Write",
"Memory Read Multiple",
"Dual Address Cycle",
"Memory Read Line",
"Memory Write-and-Invalidate"
};
static irqreturn_t st40_pci_irq(int irq, void *dev_instance)
{
unsigned pci_int, pci_air, pci_cir, pci_aint;
static int count=0;
pci_int = ST40PCI_READ(INT);pci_aint = ST40PCI_READ(AINT);
pci_cir = ST40PCI_READ(CIR);pci_air = ST40PCI_READ(AIR);
/* Reset state to stop multiple interrupts */
ST40PCI_WRITE(INT, ~0); ST40PCI_WRITE(AINT, ~0);
if(++count>1) return IRQ_HANDLED;
printk("** PCI ERROR **\n");
if(pci_int) {
printk("** INT register status\n");
print_pci_errors(pci_int,int_error,NUM_PCI_INT_ERRS);
}
if(pci_aint) {
printk("** AINT register status\n");
print_pci_errors(pci_aint,aint_error,NUM_PCI_AINT_ERRS);
}
printk("** Address and command info\n");
printk("** Command %s : Address 0x%x\n",
pci_commands[pci_cir&0xf],pci_air);
if(pci_cir&CIR_PIOTEM) {
printk("CIR_PIOTEM:PIO transfer error for master\n");
}
if(pci_cir&CIR_RWTET) {
printk("CIR_RWTET:Read/Write transfer error for target\n");
}
return IRQ_HANDLED;
}
/* Rounds a number UP to the nearest power of two. Used for
* sizing the PCI window.
*/
static u32 r2p2(u32 num)
{
int i = 31;
u32 tmp = num;
if (num == 0)
return 0;
do {
if (tmp & (1 << 31))
break;
i--;
tmp <<= 1;
} while (i >= 0);
tmp = 1 << i;
/* If the original number isn't a power of 2, round it up */
if (tmp != num)
tmp <<= 1;
return tmp;
}
static void __init pci_fixup_ide_bases(struct pci_dev *d)
{
int i;
/*
* PCI IDE controllers use non-standard I/O port decoding, respect it.
*/
if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
return;
printk("PCI: IDE base address fixup for %s\n", pci_name(d));
for(i=0; i<4; i++) {
struct resource *r = &d->resource[i];
if ((r->start & ~0x80) == 0x374) {
r->start |= 2;
r->end = r->start;
}
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
int __init st40pci_init(unsigned memStart, unsigned memSize)
{
u32 lsr0;
SetPCIPLL();
/* Initialises the ST40 pci subsystem, performing a reset, then programming
* up the address space decoders appropriately
*/
/* Should reset core here as well methink */
ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_SOFT_RESET);
/* Loop while core resets */
while (ST40PCI_READ(CR) & CR_SOFT_RESET);
/* Switch off interrupts */
ST40PCI_WRITE(INTM, 0);
ST40PCI_WRITE(AINT, 0);
/* Now, lets reset all the cards on the bus with extreme prejudice */
ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_RSTCTL);
udelay(250);
/* Set bus active, take it out of reset */
ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_BMAM | CR_CFINT | CR_PFCS | CR_PFE);
/* The PCI spec says that no access must be made to the bus until 1 second
* after reset. This seem ludicrously long, but some delay is needed here
*/
mdelay(1000);
/* Switch off interrupts */
ST40PCI_WRITE(INTM, 0);
ST40PCI_WRITE(AINT, 0);
/* Allow it to be a master */
ST40PCI_WRITE_SHORT(CSR_CMD,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
PCI_COMMAND_IO);
/* Access to the 0xb0000000 -> 0xb6000000 area will go through to 0x10000000 -> 0x16000000
* on the PCI bus. This allows a nice 1-1 bus to phys mapping.
*/
ST40PCI_WRITE(MBR, 0x10000000);
/* Always set the max size 128M (actually, it is only 96MB wide) */
ST40PCI_WRITE(MBMR, 0x07ff0000);
/* I/O addresses are mapped at 0xb6000000 -> 0xb7000000. These are changed to 0, to
* allow cards that have legacy io such as vga to function correctly. This gives a
* maximum of 64K of io/space as only the bottom 16 bits of the address are copied
* over to the bus when the transaction is made. 64K of io space is more than enough
*/
ST40PCI_WRITE(IOBR, 0x0);
/* Set up the 64K window */
ST40PCI_WRITE(IOBMR, 0x0);
/* Now we set up the mbars so the PCI bus can see the local memory */
/* Expose a 256M window starting at PCI address 0... */
ST40PCI_WRITE(CSR_MBAR0, 0);
ST40PCI_WRITE(LSR0, 0x0fff0001);
/* ... and set up the initial incoming window to expose all of RAM */
pci_set_rbar_region(7, memStart, memStart, memSize);
/* Maximise timeout values */
ST40PCI_WRITE_BYTE(CSR_TRDY, 0xff);
ST40PCI_WRITE_BYTE(CSR_RETRY, 0xff);
ST40PCI_WRITE_BYTE(CSR_MIT, 0xff);
ST40PCI_WRITE_BYTE(PERF,PERF_MASTER_WRITE_POSTING);
return 1;
}
char * __devinit pcibios_setup(char *str)
{
return str;
}
#define SET_CONFIG_BITS(bus,devfn,where)\
(((bus) << 16) | ((devfn) << 8) | ((where) & ~3) | (bus!=0))
#define CONFIG_CMD(bus, devfn, where) SET_CONFIG_BITS(bus->number,devfn,where)
static int CheckForMasterAbort(void)
{
if (ST40PCI_READ(INT) & INT_MADIM) {
/* Should we clear config space version as well ??? */
ST40PCI_WRITE(INT, INT_MADIM);
ST40PCI_WRITE_SHORT(CSR_STATUS, 0);
return 1;
}
return 0;
}
/* Write to config register */
static int st40pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
{
ST40PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
switch (size) {
case 1:
*val = (u8)ST40PCI_READ_BYTE(PDR + (where & 3));
break;
case 2:
*val = (u16)ST40PCI_READ_SHORT(PDR + (where & 2));
break;
case 4:
*val = ST40PCI_READ(PDR);
break;
}
if (CheckForMasterAbort()){
switch (size) {
case 1:
*val = (u8)0xff;
break;
case 2:
*val = (u16)0xffff;
break;
case 4:
*val = 0xffffffff;
break;
}
}
return PCIBIOS_SUCCESSFUL;
}
static int st40pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
{
ST40PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
switch (size) {
case 1:
ST40PCI_WRITE_BYTE(PDR + (where & 3), (u8)val);
break;
case 2:
ST40PCI_WRITE_SHORT(PDR + (where & 2), (u16)val);
break;
case 4:
ST40PCI_WRITE(PDR, val);
break;
}
CheckForMasterAbort();
return PCIBIOS_SUCCESSFUL;
}
struct pci_ops st40pci_config_ops = {
.read = st40pci_read,
.write = st40pci_write,
};
/* Everything hangs off this */
static struct pci_bus *pci_root_bus;
static int __init pcibios_init(void)
{
extern unsigned long memory_start, memory_end;
printk(KERN_ALERT "pci-st40.c: pcibios_init\n");
if (sh_mv.mv_init_pci != NULL) {
sh_mv.mv_init_pci();
}
/* The pci subsytem needs to know where memory is and how much
* of it there is. I've simply made these globals. A better mechanism
* is probably needed.
*/
st40pci_init(PHYSADDR(memory_start),
PHYSADDR(memory_end) - PHYSADDR(memory_start));
if (request_irq(ST40PCI_ERR_IRQ, st40_pci_irq,
IRQF_DISABLED, "st40pci", NULL)) {
printk(KERN_ERR "st40pci: Cannot hook interrupt\n");
return -EIO;
}
/* Enable the PCI interrupts on the device */
ST40PCI_WRITE(INTM, ~0);
ST40PCI_WRITE(AINT, ~0);
/* Map the io address apprioately */
#ifdef CONFIG_HD64465
hd64465_port_map(PCIBIOS_MIN_IO, (64 * 1024) - PCIBIOS_MIN_IO + 1,
ST40_IO_ADDR + PCIBIOS_MIN_IO, 0);
#endif
/* ok, do the scan man */
pci_root_bus = pci_scan_bus(0, &st40pci_config_ops, NULL);
pci_assign_unassigned_resources();
return 0;
}
subsys_initcall(pcibios_init);
/*
* Publish a region of local address space over the PCI bus
* to other devices.
*/
static void pci_set_rbar_region(unsigned int region, unsigned long localAddr,
unsigned long pciOffset, unsigned long regionSize)
{
unsigned long mask;
if (region > 7)
return;
if (regionSize > (512 * 1024 * 1024))
return;
mask = r2p2(regionSize) - 0x10000;
/* Disable the region (in case currently in use, should never happen) */
ST40PCI_WRITE_INDEXED(RSR, region, 0);
/* Start of local address space to publish */
ST40PCI_WRITE_INDEXED(RLAR, region, PHYSADDR(localAddr) );
/* Start of region in PCI address space as an offset from MBAR0 */
ST40PCI_WRITE_INDEXED(RBAR, region, pciOffset);
/* Size of region */
ST40PCI_WRITE_INDEXED(RSR, region, mask | 1);
}

136
arch/sh/drivers/pci/pci-st40.h
View File

@ -1,136 +0,0 @@
/*
* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Definitions for the ST40 PCI hardware.
*/
#ifndef __PCI_ST40_H__
#define __PCI_ST40_H__
#define ST40PCI_VCR_STATUS 0x00
#define ST40PCI_VCR_VERSION 0x08
#define ST40PCI_CR 0x10
#define CR_SOFT_RESET (1<<12)
#define CR_PFCS (1<<11)
#define CR_PFE (1<<9)
#define CR_BMAM (1<<6)
#define CR_HOST (1<<5)
#define CR_CLKEN (1<<4)
#define CR_SOCS (1<<3)
#define CR_IOCS (1<<2)
#define CR_RSTCTL (1<<1)
#define CR_CFINT (1<<0)
#define CR_LOCK_MASK 0x5a000000
#define ST40PCI_LSR0 0X14
#define ST40PCI_LAR0 0x1c
#define ST40PCI_INT 0x24
#define INT_MNLTDIM (1<<15)
#define INT_TTADI (1<<14)
#define INT_TMTO (1<<9)
#define INT_MDEI (1<<8)
#define INT_APEDI (1<<7)
#define INT_SDI (1<<6)
#define INT_DPEITW (1<<5)
#define INT_PEDITR (1<<4)
#define INT_TADIM (1<<3)
#define INT_MADIM (1<<2)
#define INT_MWPDI (1<<1)
#define INT_MRDPEI (1<<0)
#define ST40PCI_INTM 0x28
#define ST40PCI_AIR 0x2c
#define ST40PCI_CIR 0x30
#define CIR_PIOTEM (1<<31)
#define CIR_RWTET (1<<26)
#define ST40PCI_AINT 0x40
#define AINT_MBI (1<<13)
#define AINT_TBTOI (1<<12)
#define AINT_MBTOI (1<<11)
#define AINT_TAI (1<<3)
#define AINT_MAI (1<<2)
#define AINT_RDPEI (1<<1)
#define AINT_WDPE (1<<0)
#define ST40PCI_AINTM 0x44
#define ST40PCI_BMIR 0x48
#define ST40PCI_PAR 0x4c
#define ST40PCI_MBR 0x50
#define ST40PCI_IOBR 0x54
#define ST40PCI_PINT 0x58
#define ST40PCI_PINTM 0x5c
#define ST40PCI_MBMR 0x70
#define ST40PCI_IOBMR 0x74
#define ST40PCI_PDR 0x78
/* H8 specific registers start here */
#define ST40PCI_WCBAR 0x7c
#define ST40PCI_LOCCFG_UNLOCK 0x34
#define ST40PCI_RBAR0 0x100
#define ST40PCI_RSR0 0x104
#define ST40PCI_RLAR0 0x108
#define ST40PCI_RBAR1 0x110
#define ST40PCI_RSR1 0x114
#define ST40PCI_RLAR1 0x118
#define ST40PCI_RBAR2 0x120
#define ST40PCI_RSR2 0x124
#define ST40PCI_RLAR2 0x128
#define ST40PCI_RBAR3 0x130
#define ST40PCI_RSR3 0x134
#define ST40PCI_RLAR3 0x138
#define ST40PCI_RBAR4 0x140
#define ST40PCI_RSR4 0x144
#define ST40PCI_RLAR4 0x148
#define ST40PCI_RBAR5 0x150
#define ST40PCI_RSR5 0x154
#define ST40PCI_RLAR5 0x158
#define ST40PCI_RBAR6 0x160
#define ST40PCI_RSR6 0x164
#define ST40PCI_RLAR6 0x168
#define ST40PCI_RBAR7 0x170
#define ST40PCI_RSR7 0x174
#define ST40PCI_RLAR7 0x178
#define ST40PCI_RBAR(n) (0x100+(0x10*(n)))
#define ST40PCI_RSR(n) (0x104+(0x10*(n)))
#define ST40PCI_RLAR(n) (0x108+(0x10*(n)))
#define ST40PCI_PERF 0x80
#define PERF_MASTER_WRITE_POSTING (1<<4)
/* H8 specific registers end here */
/* These are configs space registers */
#define ST40PCI_CSR_VID 0x10000
#define ST40PCI_CSR_DID 0x10002
#define ST40PCI_CSR_CMD 0x10004
#define ST40PCI_CSR_STATUS 0x10006
#define ST40PCI_CSR_MBAR0 0x10010
#define ST40PCI_CSR_TRDY 0x10040
#define ST40PCI_CSR_RETRY 0x10041
#define ST40PCI_CSR_MIT 0x1000d
#define ST40_IO_ADDR 0xb6000000
#endif /* __PCI_ST40_H__ */

3
arch/sh/kernel/Makefile
View File

@ -10,7 +10,6 @@ obj-y := debugtraps.o io.o io_generic.o irq.o machvec.o process.o ptrace.o \
obj-y += cpu/ timers/
obj-$(CONFIG_VSYSCALL) += vsyscall/
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_CF_ENABLER) += cf-enabler.o
obj-$(CONFIG_SH_STANDARD_BIOS) += sh_bios.o
@ -22,3 +21,5 @@ obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_STACKTRACE) += stacktrace.o
EXTRA_CFLAGS += -Werror

2
arch/sh/kernel/cpu/sh3/ex.S
View File

@ -46,7 +46,7 @@ ENTRY(exception_handling_table)
.long exception_error ! illegal_slot_instruction (filled by trap_init) /*1A0*/
ENTRY(nmi_slot)
#if defined (CONFIG_KGDB_NMI)
.long debug_enter /* 1C0 */ ! Allow trap to debugger
.long kgdb_handle_exception /* 1C0 */ ! Allow trap to debugger
#else
.long exception_none /* 1C0 */ ! Not implemented yet
#endif

8
arch/sh/kernel/cpu/sh4/probe.c
View File

@ -139,14 +139,6 @@ int __init detect_cpu_and_cache_system(void)
boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
CPU_HAS_LLSC;
break;
case 0x8000:
boot_cpu_data.type = CPU_ST40RA;
boot_cpu_data.flags |= CPU_HAS_FPU;
break;
case 0x8100:
boot_cpu_data.type = CPU_ST40GX1;
boot_cpu_data.flags |= CPU_HAS_FPU;
break;
case 0x700:
boot_cpu_data.type = CPU_SH4_501;
boot_cpu_data.icache.ways = 2;

1
arch/sh/kernel/irq.c
View File

@ -11,7 +11,6 @@
#include <linux/module.h>
#include <linux/kernel_stat.h>
#include <linux/seq_file.h>
#include <linux/irq.h>
#include <asm/processor.h>
#include <asm/machvec.h>
#include <asm/uaccess.h>

9
arch/sh/kernel/kgdb_stub.c
View File

@ -102,6 +102,7 @@
#include <linux/init.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/module.h>
#include <asm/system.h>
#include <asm/cacheflush.h>
#include <asm/current.h>
@ -116,7 +117,9 @@ kgdb_debug_hook_t *kgdb_debug_hook;
kgdb_bus_error_hook_t *kgdb_bus_err_hook;
int (*kgdb_getchar)(void);
EXPORT_SYMBOL_GPL(kgdb_getchar);
void (*kgdb_putchar)(int);
EXPORT_SYMBOL_GPL(kgdb_putchar);
static void put_debug_char(int c)
{
@ -136,7 +139,7 @@ static int get_debug_char(void)
#define NUMREGBYTES (MAXREG*4)
#define OUTBUFMAX (NUMREGBYTES*2+512)
enum regs {
enum {
R0 = 0, R1, R2, R3, R4, R5, R6, R7,
R8, R9, R10, R11, R12, R13, R14, R15,
PC, PR, GBR, VBR, MACH, MACL, SR,
@ -176,9 +179,13 @@ int kgdb_nofault; /* Boolean to ignore bus errs (i.e. in GDB) */
/* SCI/UART settings, used in kgdb_console_setup() */
int kgdb_portnum = CONFIG_KGDB_DEFPORT;
EXPORT_SYMBOL_GPL(kgdb_portnum);
int kgdb_baud = CONFIG_KGDB_DEFBAUD;
EXPORT_SYMBOL_GPL(kgdb_baud);
char kgdb_parity = CONFIG_KGDB_DEFPARITY;
EXPORT_SYMBOL_GPL(kgdb_parity);
char kgdb_bits = CONFIG_KGDB_DEFBITS;
EXPORT_SYMBOL_GPL(kgdb_bits);
/* Jump buffer for setjmp/longjmp */
static jmp_buf rem_com_env;

1
arch/sh/kernel/setup.c
View File

@ -303,7 +303,6 @@ static const char *cpu_name[] = {
[CPU_SH7750S] = "SH7750S", [CPU_SH7750R] = "SH7750R",
[CPU_SH7751] = "SH7751", [CPU_SH7751R] = "SH7751R",
[CPU_SH7760] = "SH7760",
[CPU_ST40RA] = "ST40RA", [CPU_ST40GX1] = "ST40GX1",
[CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
[CPU_SH7770] = "SH7770", [CPU_SH7780] = "SH7780",
[CPU_SH7781] = "SH7781", [CPU_SH7343] = "SH7343",

2
arch/sh/kernel/sh_ksyms.c
View File

@ -106,7 +106,6 @@ DECLARE_EXPORT(__movmem);
DECLARE_EXPORT(__movstr);
#endif
#ifdef CONFIG_CPU_SH4
#if __GNUC__ == 4
DECLARE_EXPORT(__movmem_i4_even);
DECLARE_EXPORT(__movmem_i4_odd);
@ -126,7 +125,6 @@ DECLARE_EXPORT(__movstr_i4_even);
DECLARE_EXPORT(__movstr_i4_odd);
DECLARE_EXPORT(__movstrSI12_i4);
#endif /* __GNUC__ == 4 */
#endif
#if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \
defined(CONFIG_SH7705_CACHE_32KB))

2
arch/sh/lib/Makefile
View File

@ -9,3 +9,5 @@ memcpy-y := memcpy.o
memcpy-$(CONFIG_CPU_SH4) := memcpy-sh4.o
lib-y += $(memcpy-y)
EXTRA_CFLAGS += -Werror

21
arch/sh/mm/Kconfig
View File

@ -17,7 +17,7 @@ config CPU_SH4
bool
select CPU_HAS_INTEVT
select CPU_HAS_SR_RB
select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2
select CPU_HAS_PTEA if !CPU_SH4A || CPU_SHX2
select CPU_HAS_FPU if !CPU_SH4AL_DSP
config CPU_SH4A
@ -29,10 +29,6 @@ config CPU_SH4AL_DSP
select CPU_SH4A
select CPU_HAS_DSP
config CPU_SUBTYPE_ST40
bool
select CPU_SH4
config CPU_SHX2
bool
@ -152,21 +148,6 @@ config CPU_SUBTYPE_SH4_202
bool "Support SH4-202 processor"
select CPU_SH4
# ST40 Processor Support
config CPU_SUBTYPE_ST40STB1
bool "Support ST40STB1/ST40RA processors"
select CPU_SUBTYPE_ST40
help
Select ST40STB1 if you have a ST40RA CPU.
This was previously called the ST40STB1, hence the option name.
config CPU_SUBTYPE_ST40GX1
bool "Support ST40GX1 processor"
select CPU_SUBTYPE_ST40
help
Select ST40GX1 if you have a ST40GX1 CPU.
# SH-4A Processor Support
config CPU_SUBTYPE_SH7770

2
arch/sh/mm/Makefile
View File

@ -33,3 +33,5 @@ endif
obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
obj-$(CONFIG_32BIT) += pmb.o
obj-$(CONFIG_NUMA) += numa.o
EXTRA_CFLAGS += -Werror

45
arch/sh/mm/clear_page.S
View File

@ -150,48 +150,3 @@ ENTRY(__clear_user)
.long 8b, .Lbad_clear_user
.long 9b, .Lbad_clear_user
.previous
#if defined(CONFIG_CPU_SH4)
/*
* __clear_user_page
* @to: P3 address (with same color)
* @orig_to: P1 address
*
* void __clear_user_page(void *to, void *orig_to)
*/
/*
* r0 --- scratch
* r4 --- to
* r5 --- orig_to
* r6 --- to + PAGE_SIZE
*/
ENTRY(__clear_user_page)
mov.l .Lpsz,r0
mov r4,r6
add r0,r6
mov #0,r0
!
1: ocbi @r5
add #32,r5
movca.l r0,@r4
mov r4,r1
add #32,r4
mov.l r0,@-r4
mov.l r0,@-r4
mov.l r0,@-r4
mov.l r0,@-r4
mov.l r0,@-r4
mov.l r0,@-r4
mov.l r0,@-r4
add #28,r4
cmp/eq r6,r4
bf/s 1b
ocbwb @r1
!
rts
nop
.Lpsz: .long PAGE_SIZE
#endif

61
arch/sh/mm/copy_page.S
View File

@ -68,67 +68,6 @@ ENTRY(copy_page_slow)
rts
nop
#if defined(CONFIG_CPU_SH4)
/*
* __copy_user_page
* @to: P1 address (with same color)
* @from: P1 address
* @orig_to: P1 address
*
* void __copy_user_page(void *to, void *from, void *orig_to)
*/
/*
* r0, r1, r2, r3, r4, r5, r6, r7 --- scratch
* r8 --- from + PAGE_SIZE
* r9 --- orig_to
* r10 --- to
* r11 --- from
*/
ENTRY(__copy_user_page)
mov.l r8,@-r15
mov.l r9,@-r15
mov.l r10,@-r15
mov.l r11,@-r15
mov r4,r10
mov r5,r11
mov r6,r9
mov r5,r8
mov.l .Lpsz,r0
add r0,r8
!
1: ocbi @r9
add #32,r9
mov.l @r11+,r0
mov.l @r11+,r1
mov.l @r11+,r2
mov.l @r11+,r3
mov.l @r11+,r4
mov.l @r11+,r5
mov.l @r11+,r6
mov.l @r11+,r7
movca.l r0,@r10
mov r10,r0
add #32,r10
mov.l r7,@-r10
mov.l r6,@-r10
mov.l r5,@-r10
mov.l r4,@-r10
mov.l r3,@-r10
mov.l r2,@-r10
mov.l r1,@-r10
ocbwb @r0
cmp/eq r11,r8
bf/s 1b
add #28,r10
!
mov.l @r15+,r11
mov.l @r15+,r10
mov.l @r15+,r9
mov.l @r15+,r8
rts
nop
#endif
.align 2
.Lpsz: .long PAGE_SIZE
/*

75
arch/sh/mm/pg-sh4.c
View File

@ -9,6 +9,8 @@
#include <linux/mm.h>
#include <linux/mutex.h>
#include <linux/fs.h>
#include <linux/highmem.h>
#include <linux/module.h>
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>
@ -50,35 +52,62 @@ static inline void kunmap_coherent(struct page *page)
void clear_user_page(void *to, unsigned long address, struct page *page)
{
__set_bit(PG_mapped, &page->flags);
if (((address ^ (unsigned long)to) & CACHE_ALIAS) == 0)
clear_page(to);
else {
void *vto = kmap_coherent(page, address);
__clear_user_page(vto, to);
kunmap_coherent(vto);
}
clear_page(to);
if ((((address & PAGE_MASK) ^ (unsigned long)to) & CACHE_ALIAS))
__flush_wback_region(to, PAGE_SIZE);
}
/*
* copy_user_page
* @to: P1 address
* @from: P1 address
* @address: U0 address to be mapped
* @page: page (virt_to_page(to))
*/
void copy_user_page(void *to, void *from, unsigned long address,
struct page *page)
void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
unsigned long vaddr, void *dst, const void *src,
unsigned long len)
{
void *vto;
__set_bit(PG_mapped, &page->flags);
if (((address ^ (unsigned long)to) & CACHE_ALIAS) == 0)
copy_page(to, from);
else {
void *vfrom = kmap_coherent(page, address);
__copy_user_page(vfrom, from, to);
kunmap_coherent(vfrom);
}
vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
memcpy(vto, src, len);
kunmap_coherent(vto);
if (vma->vm_flags & VM_EXEC)
flush_cache_page(vma, vaddr, page_to_pfn(page));
}
void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
unsigned long vaddr, void *dst, const void *src,
unsigned long len)
{
void *vfrom;
__set_bit(PG_mapped, &page->flags);
vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
memcpy(dst, vfrom, len);
kunmap_coherent(vfrom);
}
void copy_user_highpage(struct page *to, struct page *from,
unsigned long vaddr, struct vm_area_struct *vma)
{
void *vfrom, *vto;
__set_bit(PG_mapped, &to->flags);
vto = kmap_atomic(to, KM_USER1);
vfrom = kmap_coherent(from, vaddr);
copy_page(vto, vfrom);
kunmap_coherent(vfrom);
if (((vaddr ^ (unsigned long)vto) & CACHE_ALIAS))
__flush_wback_region(vto, PAGE_SIZE);
kunmap_atomic(vto, KM_USER1);
/* Make sure this page is cleared on other CPU's too before using it */
smp_wmb();
}
EXPORT_SYMBOL(copy_user_highpage);
/*
* For SH-4, we have our own implementation for ptep_get_and_clear
*/

1
arch/sh/oprofile/Makefile
View File

@ -15,3 +15,4 @@ profdrvr-$(CONFIG_CPU_SUBTYPE_SH7091) := op_model_sh7750.o
oprofile-y := $(DRIVER_OBJS) $(profdrvr-y)
EXTRA_CFLAGS += -Werror

10
arch/sh64/kernel/process.c
View File

@ -26,6 +26,7 @@
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/proc_fs.h>
#include <asm/uaccess.h>
#include <asm/pgtable.h>
@ -656,9 +657,6 @@ unsigned long get_wchan(struct task_struct *p)
*/
#if defined(CONFIG_SH64_PROC_ASIDS)
#include <linux/init.h>
#include <linux/proc_fs.h>
static int
asids_proc_info(char *buf, char **start, off_t fpos, int length, int *eof, void *data)
{
@ -686,10 +684,8 @@ asids_proc_info(char *buf, char **start, off_t fpos, int length, int *eof, void
static int __init register_proc_asids(void)
{
create_proc_read_entry("asids", 0, NULL, asids_proc_info, NULL);
return 0;
create_proc_read_entry("asids", 0, NULL, asids_proc_info, NULL);
return 0;
}
__initcall(register_proc_asids);
#endif

5
arch/sh64/kernel/traps.c
View File

@ -30,7 +30,6 @@
#include <linux/interrupt.h>
#include <linux/sysctl.h>
#include <linux/module.h>
#include <asm/system.h>
#include <asm/uaccess.h>
#include <asm/io.h>
@ -242,9 +241,6 @@ DO_ERROR(12, SIGILL, "reserved instruction", reserved_inst, current)
#endif /* CONFIG_SH64_ID2815_WORKAROUND */
#include <asm/system.h>
/* Called with interrupts disabled */
asmlinkage void do_exception_error(unsigned long ex, struct pt_regs *regs)
{
@ -984,4 +980,3 @@ asmlinkage void do_debug_interrupt(unsigned long code, struct pt_regs *regs)
/* Clear all DEBUGINT causes */
poke_real_address_q(DM_EXP_CAUSE_PHY, 0x0);
}

6
drivers/rtc/rtc-sh.c
View File

@ -351,8 +351,10 @@ static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm)
tm->tm_sec, tm->tm_min, tm->tm_hour,
tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday);
if (rtc_valid_tm(tm) < 0)
if (rtc_valid_tm(tm) < 0) {
dev_err(dev, "invalid date\n");
rtc_time_to_tm(0, tm);
}
return 0;
}
@ -588,7 +590,7 @@ static int __devinit sh_rtc_probe(struct platform_device *pdev)
rtc->rtc_dev = rtc_device_register("sh", &pdev->dev,
&sh_rtc_ops, THIS_MODULE);
if (IS_ERR(rtc)) {
if (IS_ERR(rtc->rtc_dev)) {
ret = PTR_ERR(rtc->rtc_dev);
goto err_badmap;
}

19
drivers/serial/sh-sci.h
View File

@ -77,7 +77,6 @@
# define SCIF_ONLY
#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
# define SCI_NPORTS 2
# define SCIF_ORER 0x0001 /* overrun error bit */
# define PACR 0xa4050100
# define PBCR 0xa4050102
@ -102,12 +101,6 @@
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
# define SCIF_ONLY
#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
# define SCSPTR1 0xffe00020 /* 16 bit SCIF */
# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
# define SCIF_ONLY
#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
# include <asm/hardware.h>
# define SCIF_BASE_ADDR 0x01030000
@ -116,8 +109,7 @@
# define SCIF_LSR2_OFFS 0x0000024
# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,
TE=1,RE=1,REIE=1 */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
# define SCIF_ONLY
#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
@ -577,15 +569,6 @@ static inline int sci_rxd_in(struct uart_port *port)
return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xffe00000)
return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */
else
return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
}
#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
static inline int sci_rxd_in(struct uart_port *port)
{

7
drivers/sh/superhyway/superhyway.c
View File

@ -107,16 +107,17 @@ int superhyway_add_devices(struct superhyway_bus *bus,
static int __init superhyway_init(void)
{
struct superhyway_bus *bus;
int ret = 0;
int ret;
device_register(&superhyway_bus_device);
ret = device_register(&superhyway_bus_device);
if (unlikely(ret))
return ret;
for (bus = superhyway_channels; bus->ops; bus++)
ret |= superhyway_scan_bus(bus);
return ret;
}
postcore_initcall(superhyway_init);
static const struct superhyway_device_id *

18
include/asm-sh/cacheflush.h
View File

@ -43,21 +43,31 @@ extern void __flush_purge_region(void *start, int size);
extern void __flush_invalidate_region(void *start, int size);
#endif
#define flush_cache_vmap(start, end) flush_cache_all()
#define flush_cache_vunmap(start, end) flush_cache_all()
#ifdef CONFIG_CPU_SH4
extern void copy_to_user_page(struct vm_area_struct *vma,
struct page *page, unsigned long vaddr, void *dst, const void *src,
unsigned long len);
#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
extern void copy_from_user_page(struct vm_area_struct *vma,
struct page *page, unsigned long vaddr, void *dst, const void *src,
unsigned long len);
#else
#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
do { \
flush_cache_page(vma, vaddr, page_to_pfn(page));\
memcpy(dst, src, len); \
flush_icache_user_range(vma, page, vaddr, len); \
} while (0)
#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
do { \
flush_cache_page(vma, vaddr, page_to_pfn(page));\
memcpy(dst, src, len); \
} while (0)
#endif
#define flush_cache_vmap(start, end) flush_cache_all()
#define flush_cache_vunmap(start, end) flush_cache_all()
#define HAVE_ARCH_UNMAPPED_AREA

6
include/asm-sh/cpu-sh3/timer.h
View File

@ -23,8 +23,7 @@
* ---------------------------------------------------------------------------
*/
#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
!defined(CONFIG_CPU_SUBTYPE_SH7727)
#if !defined(CONFIG_CPU_SUBTYPE_SH7720)
#define TMU_TOCR 0xfffffe90 /* Byte access */
#endif
@ -58,8 +57,7 @@
#define TMU2_TCOR 0xfffffeac /* Long access */
#define TMU2_TCNT 0xfffffeb0 /* Long access */
#define TMU2_TCR 0xfffffeb4 /* Word access */
#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
!defined(CONFIG_CPU_SUBTYPE_SH7727)
#if !defined(CONFIG_CPU_SUBTYPE_SH7720)
#define TMU2_TCPR2 0xfffffeb8 /* Long access */
#endif
#endif

11
include/asm-sh/page.h
View File

@ -73,10 +73,13 @@ extern void copy_page_nommu(void *to, void *from);
#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) && \
(defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB))
struct page;
extern void clear_user_page(void *to, unsigned long address, struct page *pg);
extern void copy_user_page(void *to, void *from, unsigned long address, struct page *pg);
extern void __clear_user_page(void *to, void *orig_to);
extern void __copy_user_page(void *to, void *from, void *orig_to);
struct vm_area_struct;
extern void clear_user_page(void *to, unsigned long address, struct page *page);
#ifdef CONFIG_CPU_SH4
extern void copy_user_highpage(struct page *to, struct page *from,
unsigned long vaddr, struct vm_area_struct *vma);
#define __HAVE_ARCH_COPY_USER_HIGHPAGE
#endif
#else
#define clear_user_page(page, vaddr, pg) clear_page(page)
#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)

4
include/asm-sh/pgtable.h
View File

@ -322,7 +322,9 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
#define PAGE_KERNEL __pgprot(0)
#define PAGE_KERNEL_NOCACHE __pgprot(0)
#define PAGE_KERNEL_RO __pgprot(0)
#define PAGE_KERNEL_PCC __pgprot(0)
#define PAGE_KERNEL_PCC(slot, type) \
__pgprot(0)
#endif
#endif /* __ASSEMBLY__ */

2
include/asm-sh/processor.h
View File

@ -49,7 +49,7 @@ enum cpu_type {
/* SH-4 types */
CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501,
CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
/* SH-4A types */
CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3,

3
include/asm-sh/ptrace.h
View File

@ -42,9 +42,6 @@
#define REG_FPSCR 55
#define REG_FPUL 56
/* options set using PTRACE_SETOPTIONS */
#define PTRACE_O_TRACESYSGOOD 0x00000001
/*
* This struct defines the way the registers are stored on the
* kernel stack during a system call or other kernel entry.

6
include/asm-sh/vga.h Normal file
View File

@ -0,0 +1,6 @@
#ifndef __ASM_SH_VGA_H
#define __ASM_SH_VGA_H
/* Stupid drivers. */
#endif /* __ASM_SH_VGA_H */

2
include/asm-sh64/ptrace.h
View File

@ -32,6 +32,4 @@ struct pt_regs {
extern void show_regs(struct pt_regs *);
#endif
#define PTRACE_O_TRACESYSGOOD 0x00000001
#endif /* __ASM_SH64_PTRACE_H */