mirror of https://gitee.com/openkylin/linux.git
brcm80211: smac: use bcma core control functions
BCMA provides functions to control the state of the cores so using that and remove similar implementation from the driver. Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com> Reviewed-by: Alwin Beukers <alwin@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Franky Lin <frankyl@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -535,36 +535,6 @@ uint ai_corerev(struct si_pub *sih)
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return (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
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}
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bool ai_iscoreup(struct si_pub *sih)
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{
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struct si_info *sii;
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struct aidmp *ai;
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sii = (struct si_info *)sih;
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ai = sii->curwrap;
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return (((R_REG(&ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) ==
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SICF_CLOCK_EN)
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&& ((R_REG(&ai->resetctrl) & AIRC_RESET) == 0));
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}
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u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val)
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{
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struct si_info *sii;
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struct aidmp *ai;
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u32 w;
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sii = (struct si_info *)sih;
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ai = sii->curwrap;
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if (mask || val) {
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w = ((R_REG(&ai->ioctrl) & ~mask) | val);
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W_REG(&ai->ioctrl, w);
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}
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return R_REG(&ai->ioctrl);
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}
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/* return true if PCIE capability exists in the pci config space */
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static bool ai_ispcie(struct si_info *sii)
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{
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@ -587,23 +557,6 @@ static bool ai_buscore_prep(struct si_info *sii)
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return true;
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}
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u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val)
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{
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struct si_info *sii;
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struct aidmp *ai;
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u32 w;
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sii = (struct si_info *)sih;
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ai = sii->curwrap;
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if (mask || val) {
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w = ((R_REG(&ai->iostatus) & ~mask) | val);
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W_REG(&ai->iostatus, w);
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}
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return R_REG(&ai->iostatus);
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}
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static bool
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ai_buscore_setup(struct si_info *sii, u32 savewin, uint *origidx)
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{
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@ -1037,61 +990,6 @@ uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val)
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return w;
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}
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void ai_core_disable(struct si_pub *sih, u32 bits)
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{
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struct si_info *sii;
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u32 dummy;
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struct aidmp *ai;
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sii = (struct si_info *)sih;
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ai = sii->curwrap;
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/* if core is already in reset, just return */
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if (R_REG(&ai->resetctrl) & AIRC_RESET)
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return;
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W_REG(&ai->ioctrl, bits);
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dummy = R_REG(&ai->ioctrl);
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udelay(10);
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W_REG(&ai->resetctrl, AIRC_RESET);
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udelay(1);
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}
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/* reset and re-enable a core
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* inputs:
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* bits - core specific bits that are set during and after reset sequence
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* resetbits - core specific bits that are set only during reset sequence
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*/
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void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits)
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{
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struct si_info *sii;
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struct aidmp *ai;
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u32 dummy;
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sii = (struct si_info *)sih;
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ai = sii->curwrap;
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/*
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* Must do the disable sequence first to work
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* for arbitrary current core state.
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*/
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ai_core_disable(sih, (bits | resetbits));
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/*
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* Now do the initialization sequence.
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*/
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W_REG(&ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN));
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dummy = R_REG(&ai->ioctrl);
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W_REG(&ai->resetctrl, 0);
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udelay(1);
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W_REG(&ai->ioctrl, (bits | SICF_CLOCK_EN));
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dummy = R_REG(&ai->ioctrl);
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udelay(1);
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}
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/* return the slow clock source - LPO, XTAL, or PCI */
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static uint ai_slowclk_src(struct si_info *sii)
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{
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@ -221,11 +221,7 @@ struct si_info {
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/* AMBA Interconnect exported externs */
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extern uint ai_coreidx(struct si_pub *sih);
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extern uint ai_corerev(struct si_pub *sih);
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extern bool ai_iscoreup(struct si_pub *sih);
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extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
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extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
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extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
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extern void ai_core_disable(struct si_pub *sih, u32 bits);
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extern u32 ai_core_cflags(struct bcma_device *core, u32 mask, u32 val);
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/* === exported functions === */
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extern struct si_pub *ai_attach(struct bcma_bus *pbus);
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@ -581,7 +581,8 @@ struct dma_pub *dma_attach(char *name, struct si_pub *sih,
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di->msg_level = msg_level ? msg_level : &dma_msg_level;
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di->dma64 = ((ai_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64);
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di->dma64 =
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((bcma_aread32(d11core, BCMA_IOST) & SISF_DMA64) == SISF_DMA64);
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/* init dma reg info */
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di->d11core = d11core;
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@ -738,6 +738,14 @@ static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
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}
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}
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static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
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{
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struct bcma_device *core = wlc_hw->d11core;
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u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
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bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
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}
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static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
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{
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BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
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@ -746,17 +754,17 @@ static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
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if (OFF == clk) { /* clear gmode bit, put phy into reset */
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ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
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brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
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(SICF_PRST | SICF_FGC));
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udelay(1);
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ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
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brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
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udelay(1);
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} else { /* take phy out of reset */
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ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
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brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
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udelay(1);
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ai_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
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brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
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udelay(1);
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}
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@ -777,9 +785,14 @@ static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
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wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
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/* set gmode core flag */
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if (wlc_hw->sbclk && !wlc_hw->noreset)
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ai_core_cflags(wlc_hw->sih, SICF_GMODE,
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((bandunit == 0) ? SICF_GMODE : 0));
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if (wlc_hw->sbclk && !wlc_hw->noreset) {
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u32 gmode = 0;
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if (bandunit == 0)
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gmode = SICF_GMODE;
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brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
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}
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}
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/* switch to new band but leave it inactive */
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@ -1257,7 +1270,7 @@ static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode)
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/* check fast clock is available (if core is not in reset) */
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if (wlc_hw->forcefastclk && wlc_hw->clk)
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WARN_ON(!(ai_core_sflags(wlc_hw->sih, 0, 0) &
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WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
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SISF_FCLKA));
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/*
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@ -1733,18 +1746,18 @@ void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
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return;
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if (ON == clk)
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ai_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
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brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
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else
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ai_core_cflags(wlc_hw->sih, SICF_FGC, 0);
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brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
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}
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void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
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{
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if (ON == clk)
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ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
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brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
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else
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ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
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brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
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}
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void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
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@ -1764,7 +1777,7 @@ void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
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if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
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NREV_LE(wlc_hw->band->phyrev, 4)) {
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/* Set the PHY bandwidth */
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ai_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
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brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
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udelay(1);
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@ -1772,11 +1785,11 @@ void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
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brcms_b_core_phypll_reset(wlc_hw);
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/* reset the PHY */
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ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
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brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
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(SICF_PRST | SICF_PCLKE));
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phy_in_reset = true;
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} else {
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ai_core_cflags(wlc_hw->sih,
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brcms_b_core_ioctl(wlc_hw,
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(SICF_PRST | SICF_PCLKE | SICF_BWMASK),
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(SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
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}
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@ -1795,8 +1808,8 @@ static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
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u32 macintmask;
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/* Enable the d11 core before accessing it */
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if (!ai_iscoreup(wlc_hw->sih)) {
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ai_core_reset(wlc_hw->sih, 0, 0);
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if (!bcma_core_is_enabled(wlc_hw->d11core)) {
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bcma_core_enable(wlc_hw->d11core, 0);
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brcms_c_mctrl_reset(wlc_hw);
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}
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@ -1923,7 +1936,7 @@ static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
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static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
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{
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bool v, clk, xtal;
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u32 resetbits = 0, flags = 0;
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u32 flags = 0;
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xtal = wlc_hw->sbclk;
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if (!xtal)
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@ -1947,7 +1960,7 @@ static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
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(ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID))
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(void)ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
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ai_core_reset(wlc_hw->sih, flags, resetbits);
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bcma_core_enable(wlc_hw->d11core, flags);
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brcms_c_mctrl_reset(wlc_hw);
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}
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@ -1956,7 +1969,7 @@ static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
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/* put core back into reset */
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if (!clk)
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ai_core_disable(wlc_hw->sih, 0);
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bcma_core_disable(wlc_hw->d11core, 0);
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if (!xtal)
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brcms_b_xtal(wlc_hw, OFF);
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@ -1982,7 +1995,6 @@ void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
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{
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uint i;
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bool fastclk;
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u32 resetbits = 0;
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if (flags == BRCMS_USE_COREFLAGS)
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flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
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@ -1995,7 +2007,7 @@ void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
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brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
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/* reset the dma engines except first time thru */
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if (ai_iscoreup(wlc_hw->sih)) {
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if (bcma_core_is_enabled(wlc_hw->d11core)) {
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for (i = 0; i < NFIFO; i++)
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if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
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wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
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@ -2033,7 +2045,7 @@ void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
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* they may touch chipcommon as well.
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*/
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wlc_hw->clk = false;
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ai_core_reset(wlc_hw->sih, flags, resetbits);
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bcma_core_enable(wlc_hw->d11core, flags);
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wlc_hw->clk = true;
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if (wlc_hw->band && wlc_hw->band->pi)
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wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
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@ -2876,7 +2888,7 @@ static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
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brcms_b_core_phypll_ctl(wlc_hw, false);
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wlc_hw->clk = false;
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ai_core_disable(wlc_hw->sih, 0);
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bcma_core_disable(wlc_hw->d11core, 0);
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wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
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}
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@ -3234,7 +3246,7 @@ static void brcms_b_coreinit(struct brcms_c_info *wlc)
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brcms_c_gpio_init(wlc);
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sflags = ai_core_sflags(wlc_hw->sih, 0, 0);
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sflags = bcma_aread32(core, BCMA_IOST);
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if (D11REV_IS(wlc_hw->corerev, 23)) {
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if (BRCMS_ISNPHY(wlc_hw->band))
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@ -5318,7 +5330,7 @@ static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
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} else {
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/* Reset and disable the core */
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if (ai_iscoreup(wlc_hw->sih)) {
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if (bcma_core_is_enabled(wlc_hw->d11core)) {
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if (bcma_read32(wlc_hw->d11core,
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D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
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brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
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@ -437,7 +437,7 @@ wlc_phy_attach(struct shared_phy *sh, struct bcma_device *d11core,
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if (D11REV_IS(sh->corerev, 4))
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sflags = SISF_2G_PHY | SISF_5G_PHY;
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else
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sflags = ai_core_sflags(sh->sih, 0, 0);
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sflags = bcma_aread32(d11core, BCMA_IOST);
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if (bandtype == BRCM_BAND_5G) {
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if ((sflags & (SISF_5G_PHY | SISF_DB_PHY)) == 0)
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@ -761,7 +761,7 @@ void wlc_phy_init(struct brcms_phy_pub *pih, u16 chanspec)
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if (!(pi->measure_hold & PHY_HOLD_FOR_SCAN))
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pi->measure_hold |= PHY_HOLD_FOR_NOT_ASSOC;
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if (WARN(!(ai_core_sflags(pi->sh->sih, 0, 0) & SISF_FCLKA),
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if (WARN(!(bcma_aread32(pi->d11core, BCMA_IOST) & SISF_FCLKA),
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"HW error SISF_FCLKA\n"))
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return;
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