mirror of https://gitee.com/openkylin/linux.git
MIPS: Octeon: Move MSI code out of octeon-irq.c.
Put all the MSI code in one place (msi-octeon.c). This simplifies octeon-irq.c and gets rid of some ugly #ifdefs Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1484/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney
Ralf Baechle
parent
cb8f55b920
commit
a894f14d7e
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@ -10,8 +10,6 @@
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#include <linux/smp.h>
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-pexp-defs.h>
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#include <asm/octeon/cvmx-npi-defs.h>
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static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock);
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static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock);
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@ -528,90 +526,6 @@ static struct irq_chip octeon_irq_chip_ciu1 = {
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#endif
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};
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#ifdef CONFIG_PCI_MSI
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static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
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static void octeon_irq_msi_ack(unsigned int irq)
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{
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if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
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/* These chips have PCI */
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cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
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1ull << (irq - OCTEON_IRQ_MSI_BIT0));
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} else {
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/*
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* These chips have PCIe. Thankfully the ACK doesn't
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* need any locking.
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*/
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cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
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1ull << (irq - OCTEON_IRQ_MSI_BIT0));
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}
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}
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static void octeon_irq_msi_eoi(unsigned int irq)
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{
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/* Nothing needed */
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}
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static void octeon_irq_msi_enable(unsigned int irq)
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{
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if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
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/*
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* Octeon PCI doesn't have the ability to mask/unmask
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* MSI interrupts individually. Instead of
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* masking/unmasking them in groups of 16, we simple
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* assume MSI devices are well behaved. MSI
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* interrupts are always enable and the ACK is assumed
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* to be enough.
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*/
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} else {
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/* These chips have PCIe. Note that we only support
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* the first 64 MSI interrupts. Unfortunately all the
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* MSI enables are in the same register. We use
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* MSI0's lock to control access to them all.
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*/
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uint64_t en;
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unsigned long flags;
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raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
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en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
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en |= 1ull << (irq - OCTEON_IRQ_MSI_BIT0);
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cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
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cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
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raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
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}
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}
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static void octeon_irq_msi_disable(unsigned int irq)
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{
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if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
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/* See comment in enable */
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} else {
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/*
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* These chips have PCIe. Note that we only support
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* the first 64 MSI interrupts. Unfortunately all the
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* MSI enables are in the same register. We use
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* MSI0's lock to control access to them all.
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*/
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uint64_t en;
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unsigned long flags;
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raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
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en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
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en &= ~(1ull << (irq - OCTEON_IRQ_MSI_BIT0));
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cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
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cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
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raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
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}
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}
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static struct irq_chip octeon_irq_chip_msi = {
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.name = "MSI",
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.enable = octeon_irq_msi_enable,
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.disable = octeon_irq_msi_disable,
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.ack = octeon_irq_msi_ack,
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.eoi = octeon_irq_msi_eoi,
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};
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#endif
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void __init arch_init_irq(void)
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{
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int irq;
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@ -672,13 +586,6 @@ void __init arch_init_irq(void)
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set_irq_chip_and_handler(irq, chip1, handle_percpu_irq);
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}
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#ifdef CONFIG_PCI_MSI
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/* 152 - 215 PCI/PCIe MSI interrupts */
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for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_BIT63; irq++) {
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set_irq_chip_and_handler(irq, &octeon_irq_chip_msi,
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handle_percpu_irq);
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}
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#endif
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set_c0_status(0x300 << 2);
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}
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@ -249,12 +249,99 @@ static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
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return IRQ_NONE;
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}
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static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
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static void octeon_irq_msi_ack(unsigned int irq)
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{
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if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
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/* These chips have PCI */
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cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
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1ull << (irq - OCTEON_IRQ_MSI_BIT0));
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} else {
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/*
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* These chips have PCIe. Thankfully the ACK doesn't
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* need any locking.
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*/
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cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
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1ull << (irq - OCTEON_IRQ_MSI_BIT0));
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}
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}
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static void octeon_irq_msi_eoi(unsigned int irq)
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{
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/* Nothing needed */
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}
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static void octeon_irq_msi_enable(unsigned int irq)
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{
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if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
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/*
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* Octeon PCI doesn't have the ability to mask/unmask
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* MSI interrupts individually. Instead of
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* masking/unmasking them in groups of 16, we simple
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* assume MSI devices are well behaved. MSI
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* interrupts are always enable and the ACK is assumed
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* to be enough.
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*/
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} else {
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/* These chips have PCIe. Note that we only support
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* the first 64 MSI interrupts. Unfortunately all the
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* MSI enables are in the same register. We use
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* MSI0's lock to control access to them all.
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*/
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uint64_t en;
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unsigned long flags;
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raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
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en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
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en |= 1ull << (irq - OCTEON_IRQ_MSI_BIT0);
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cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
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cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
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raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
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}
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}
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static void octeon_irq_msi_disable(unsigned int irq)
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{
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if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
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/* See comment in enable */
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} else {
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/*
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* These chips have PCIe. Note that we only support
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* the first 64 MSI interrupts. Unfortunately all the
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* MSI enables are in the same register. We use
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* MSI0's lock to control access to them all.
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*/
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uint64_t en;
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unsigned long flags;
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raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
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en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
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en &= ~(1ull << (irq - OCTEON_IRQ_MSI_BIT0));
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cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
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cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
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raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
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}
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}
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static struct irq_chip octeon_irq_chip_msi = {
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.name = "MSI",
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.enable = octeon_irq_msi_enable,
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.disable = octeon_irq_msi_disable,
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.ack = octeon_irq_msi_ack,
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.eoi = octeon_irq_msi_eoi,
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};
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/*
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* Initializes the MSI interrupt handling code
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*/
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int octeon_msi_initialize(void)
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static int __init octeon_msi_initialize(void)
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{
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int irq;
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for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_BIT63; irq++) {
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set_irq_chip_and_handler(irq, &octeon_irq_chip_msi,
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handle_percpu_irq);
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}
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if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
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if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
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IRQF_SHARED,
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@ -284,5 +371,4 @@ int octeon_msi_initialize(void)
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}
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return 0;
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}
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subsys_initcall(octeon_msi_initialize);
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