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Merge series "ASoC: codecs: add wcd938x support" from Srinivas Kandagatla <srinivas.kandagatla@linaro.org>: 

This patchset adds support for Qualcomm WCD938X codec.

Qualcomm WCD9380/WCD9385 Codec is a standalone Hi-Fi audio codec IC
connected over SoundWire. This device has two SoundWire devices, RX and
TX respectively supporting 4 x ADCs, ClassH, Ear, Aux PA, 2xHPH,
7 x TX diff inputs, 8 DMICs and MBHC.

Eventhough this device has two SoundWire devices, only tx device has
access to main codec Control/Status Registers!

For codec driver to be functional it would need both tx and rx Soundwire devices
to be up and this is taken care by using device component framework and device-links
are used to ensure proper pm dependencies. Ex tx does not enter suspend
before rx or codec is suspended.

This patchset along with other SoundWire patches on the list
have been tested on SM8250 MTP device.

Thanks,
srini

Changes since v8:
 - moved Kconfig and Makefile changes to last patch as suggested by Mark
 - removed array of enums and used static entries instead. Suggested by Mark
 - return true if put succeeds, Suggested by Mark
 - removed some unneeded semi-colons in switch

Srinivas Kandagatla (9):
  ASoC: dt-bindings: wcd938x: add bindings for wcd938x
  ASoC: codecs: wcd-clsh: add new version support
  ASoC: codecs: wcd938x: add basic driver
  ASoC: dt-bindings: wcd938x-sdw: add bindings for wcd938x-sdw
  ASoC: codecs: wcd938x-sdw: add SoundWire driver
  ASoC: codecs: wcd938x: add basic controls
  ASoC: codecs: wcd938x: add playback dapm widgets
  ASoC: codecs: wcd938x: add capture dapm widgets
  ASoC: codecs: wcd938x: add audio routing and Kconfig

 .../bindings/sound/qcom,wcd938x-sdw.yaml      |   70 +
 .../bindings/sound/qcom,wcd938x.yaml          |  146 +
 sound/soc/codecs/Kconfig                      |   14 +
 sound/soc/codecs/Makefile                     |    4 +
 sound/soc/codecs/wcd-clsh-v2.c                |  348 +-
 sound/soc/codecs/wcd-clsh-v2.h                |   16 +
 sound/soc/codecs/wcd938x-sdw.c                |  315 ++
 sound/soc/codecs/wcd938x.c                    | 3753 +++++++++++++++++
 sound/soc/codecs/wcd938x.h                    |  720 ++++
 9 files changed, 5376 insertions(+), 10 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/qcom,wcd938x-sdw.yaml
 create mode 100644 Documentation/devicetree/bindings/sound/qcom,wcd938x.yaml
 create mode 100644 sound/soc/codecs/wcd938x-sdw.c
 create mode 100644 sound/soc/codecs/wcd938x.c
 create mode 100644 sound/soc/codecs/wcd938x.h

--
2.21.0
This commit is contained in:
Mark Brown 2021-06-14 14:58:52 +01:00
parent 03c0cbd946 0454422288
commit a918e29174
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
9 changed files with 5376 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

70
Documentation/devicetree/bindings/sound/qcom,wcd938x-sdw.yaml Normal file
View File

@ -0,0 +1,70 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/qcom,wcd938x-sdw.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Bindings for Qualcomm SoundWire Slave devices on WCD9380/WCD9385
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description: |
Qualcomm WCD9380/WCD9385 Codec is a standalone Hi-Fi audio codec IC.
It has RX and TX Soundwire slave devices. This bindings is for the
slave devices.
properties:
compatible:
const: sdw20217010d00
reg:
maxItems: 1
qcom,tx-port-mapping:
description: |
Specifies static port mapping between slave and master tx ports.
In the order of slave port index.
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 4
maxItems: 4
qcom,rx-port-mapping:
description: |
Specifies static port mapping between slave and master rx ports.
In the order of slave port index.
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 5
maxItems: 5
required:
- compatible
- reg
additionalProperties: false
examples:
- |
soundwire@3210000 {
#address-cells = <2>;
#size-cells = <0>;
reg = <0x03210000 0x2000>;
wcd938x_rx: codec@0,4 {
compatible = "sdw20217010d00";
reg = <0 4>;
qcom,rx-port-mapping = <1 2 3 4 5>;
};
};
soundwire@3230000 {
#address-cells = <2>;
#size-cells = <0>;
reg = <0x03230000 0x2000>;
wcd938x_tx: codec@0,3 {
compatible = "sdw20217010d00";
reg = <0 3>;
qcom,tx-port-mapping = <2 3 4 5>;
};
};
...

146
Documentation/devicetree/bindings/sound/qcom,wcd938x.yaml Normal file
View File

@ -0,0 +1,146 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/qcom,wcd938x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Bindings for Qualcomm WCD9380/WCD9385 Audio Codec
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description: |
Qualcomm WCD9380/WCD9385 Codec is a standalone Hi-Fi audio codec IC.
It has RX and TX Soundwire slave devices.
properties:
compatible:
enum:
- qcom,wcd9380-codec
- qcom,wcd9385-codec
reset-gpios:
description: GPIO spec for reset line to use
maxItems: 1
vdd-buck-supply:
description: A reference to the 1.8V buck supply
vdd-rxtx-supply:
description: A reference to the 1.8V rx supply
vdd-io-supply:
description: A reference to the 1.8V I/O supply
qcom,tx-device:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: A reference to Soundwire tx device phandle
qcom,rx-device:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: A reference to Soundwire rx device phandle
qcom,micbias1-microvolt:
description: micbias1 voltage
minimum: 1800000
maximum: 2850000
qcom,micbias2-microvolt:
description: micbias2 voltage
minimum: 1800000
maximum: 2850000
qcom,micbias3-microvolt:
description: micbias3 voltage
minimum: 1800000
maximum: 2850000
qcom,micbias4-microvolt:
description: micbias4 voltage
minimum: 1800000
maximum: 2850000
qcom,hphl-jack-type-normally-closed:
description: Indicates that HPHL jack switch type is normally closed
type: boolean
qcom,ground-jack-type-normally-closed:
description: Indicates that Headset Ground switch type is normally closed
type: boolean
qcom,mbhc-headset-vthreshold-microvolt:
description: Voltage threshold value for headset detection
minimum: 0
maximum: 2850000
qcom,mbhc-headphone-vthreshold-microvolt:
description: Voltage threshold value for headphone detection
minimum: 0
maximum: 2850000
qcom,mbhc-buttons-vthreshold-microvolt:
description:
Array of 8 Voltage threshold values corresponding to headset
button0 - button7
minItems: 8
maxItems: 8
'#sound-dai-cells':
const: 1
required:
- compatible
- reset-gpios
- qcom,tx-device
- qcom,rx-device
- qcom,micbias1-microvolt
- qcom,micbias2-microvolt
- qcom,micbias3-microvolt
- qcom,micbias4-microvolt
- "#sound-dai-cells"
additionalProperties: false
examples:
- |
codec {
compatible = "qcom,wcd9380-codec";
reset-gpios = <&tlmm 32 0>;
#sound-dai-cells = <1>;
qcom,tx-device = <&wcd938x_tx>;
qcom,rx-device = <&wcd938x_rx>;
qcom,micbias1-microvolt = <1800000>;
qcom,micbias2-microvolt = <1800000>;
qcom,micbias3-microvolt = <1800000>;
qcom,micbias4-microvolt = <1800000>;
qcom,hphl-jack-type-normally-closed;
qcom,ground-jack-type-normally-closed;
qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
};
/* ... */
soundwire@3210000 {
#address-cells = <2>;
#size-cells = <0>;
reg = <0x03210000 0x2000>;
wcd938x_rx: codec@0,4 {
compatible = "sdw20217010d00";
reg = <0 4>;
qcom,rx-port-mapping = <1 2 3 4 5>;
};
};
soundwire@3230000 {
#address-cells = <2>;
#size-cells = <0>;
reg = <0x03230000 0x2000>;
wcd938x_tx: codec@0,3 {
compatible = "sdw20217010d00";
reg = <0 3>;
qcom,tx-port-mapping = <2 3 4 5>;
};
};
...

14
sound/soc/codecs/Kconfig
View File

@ -234,6 +234,8 @@ config SND_SOC_ALL_CODECS
imply SND_SOC_UDA1380
imply SND_SOC_WCD9335
imply SND_SOC_WCD934X
imply SND_SOC_WCD937X
imply SND_SOC_WCD938X
imply SND_SOC_LPASS_RX_MACRO
imply SND_SOC_LPASS_TX_MACRO
imply SND_SOC_WL1273
@ -1554,6 +1556,18 @@ config SND_SOC_WCD934X
The WCD9340/9341 is a audio codec IC Integrated in
Qualcomm SoCs like SDM845.
config SND_SOC_WCD938X
tristate
config SND_SOC_WCD938X_SDW
tristate "WCD9380/WCD9385 Codec - SDW"
select SND_SOC_WCD938X
depends on SOUNDWIRE
select REGMAP_SOUNDWIRE
help
The WCD9380/9385 is a audio codec IC Integrated in
Qualcomm SoCs like SM8250.
config SND_SOC_WL1273
tristate

4
sound/soc/codecs/Makefile
View File

@ -255,6 +255,8 @@ snd-soc-uda1380-objs := uda1380.o
snd-soc-wcd-mbhc-objs := wcd-mbhc-v2.o
snd-soc-wcd9335-objs := wcd-clsh-v2.o wcd9335.o
snd-soc-wcd934x-objs := wcd-clsh-v2.o wcd934x.o
snd-soc-wcd938x-objs := wcd938x.o wcd-clsh-v2.o
snd-soc-wcd938x-sdw-objs := wcd938x-sdw.o
snd-soc-wl1273-objs := wl1273.o
snd-soc-wm-adsp-objs := wm_adsp.o
snd-soc-wm0010-objs := wm0010.o
@ -580,6 +582,8 @@ obj-$(CONFIG_SND_SOC_UDA1380) += snd-soc-uda1380.o
obj-$(CONFIG_SND_SOC_WCD_MBHC) += snd-soc-wcd-mbhc.o
obj-$(CONFIG_SND_SOC_WCD9335) += snd-soc-wcd9335.o
obj-$(CONFIG_SND_SOC_WCD934X) += snd-soc-wcd934x.o
obj-$(CONFIG_SND_SOC_WCD938X) += snd-soc-wcd938x.o
obj-$(CONFIG_SND_SOC_WCD938X_SDW) += snd-soc-wcd938x-sdw.o
obj-$(CONFIG_SND_SOC_WL1273) += snd-soc-wl1273.o
obj-$(CONFIG_SND_SOC_WM0010) += snd-soc-wm0010.o
obj-$(CONFIG_SND_SOC_WM1250_EV1) += snd-soc-wm1250-ev1.o

348
sound/soc/codecs/wcd-clsh-v2.c
View File

@ -88,6 +88,19 @@ struct wcd_clsh_ctrl {
#define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA 0x50
#define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_30MA 0x30
#define WCD9XXX_BASE_ADDRESS 0x3000
#define WCD9XXX_ANA_RX_SUPPLIES (WCD9XXX_BASE_ADDRESS+0x008)
#define WCD9XXX_ANA_HPH (WCD9XXX_BASE_ADDRESS+0x009)
#define WCD9XXX_CLASSH_MODE_2 (WCD9XXX_BASE_ADDRESS+0x098)
#define WCD9XXX_CLASSH_MODE_3 (WCD9XXX_BASE_ADDRESS+0x099)
#define WCD9XXX_FLYBACK_VNEG_CTRL_1 (WCD9XXX_BASE_ADDRESS+0x0A5)
#define WCD9XXX_FLYBACK_VNEG_CTRL_4 (WCD9XXX_BASE_ADDRESS+0x0A8)
#define WCD9XXX_FLYBACK_VNEGDAC_CTRL_2 (WCD9XXX_BASE_ADDRESS+0x0AF)
#define WCD9XXX_RX_BIAS_HPH_LOWPOWER (WCD9XXX_BASE_ADDRESS+0x0BF)
#define WCD9XXX_V3_RX_BIAS_FLYB_BUFF (WCD9XXX_BASE_ADDRESS+0x0C7)
#define WCD9XXX_HPH_PA_CTL1 (WCD9XXX_BASE_ADDRESS+0x0D1)
#define WCD9XXX_HPH_NEW_INT_PA_MISC2 (WCD9XXX_BASE_ADDRESS+0x138)
#define CLSH_REQ_ENABLE true
#define CLSH_REQ_DISABLE false
#define WCD_USLEEP_RANGE 50
@ -137,6 +150,20 @@ static inline void wcd_clsh_set_buck_mode(struct snd_soc_component *comp,
WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_DEFAULT);
}
static void wcd_clsh_v3_set_buck_mode(struct snd_soc_component *component,
int mode)
{
if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI ||
mode == CLS_AB_HIFI || mode == CLS_AB_LOHIFI)
snd_soc_component_update_bits(component,
WCD9XXX_ANA_RX_SUPPLIES,
0x08, 0x08); /* set to HIFI */
else
snd_soc_component_update_bits(component,
WCD9XXX_ANA_RX_SUPPLIES,
0x08, 0x00); /* set to default */
}
static inline void wcd_clsh_set_flyback_mode(struct snd_soc_component *comp,
int mode)
{
@ -170,6 +197,36 @@ static void wcd_clsh_buck_ctrl(struct wcd_clsh_ctrl *ctrl,
usleep_range(500, 500 + WCD_USLEEP_RANGE);
}
static void wcd_clsh_v3_buck_ctrl(struct snd_soc_component *component,
struct wcd_clsh_ctrl *ctrl,
int mode,
bool enable)
{
/* enable/disable buck */
if ((enable && (++ctrl->buck_users == 1)) ||
(!enable && (--ctrl->buck_users == 0))) {
snd_soc_component_update_bits(component,
WCD9XXX_ANA_RX_SUPPLIES,
(1 << 7), (enable << 7));
/*
* 500us sleep is required after buck enable/disable
* as per HW requirement
*/
usleep_range(500, 510);
if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
mode == CLS_H_HIFI || mode == CLS_H_LP)
snd_soc_component_update_bits(component,
WCD9XXX_CLASSH_MODE_3,
0x02, 0x00);
snd_soc_component_update_bits(component,
WCD9XXX_CLASSH_MODE_2,
0xFF, 0x3A);
/* 500usec delay is needed as per HW requirement */
usleep_range(500, 500 + WCD_USLEEP_RANGE);
}
}
static void wcd_clsh_flyback_ctrl(struct wcd_clsh_ctrl *ctrl,
int mode,
bool enable)
@ -219,8 +276,7 @@ static void wcd_clsh_set_gain_path(struct wcd_clsh_ctrl *ctrl, int mode)
val);
}
static void wcd_clsh_set_hph_mode(struct snd_soc_component *comp,
int mode)
static void wcd_clsh_v2_set_hph_mode(struct snd_soc_component *comp, int mode)
{
int val = 0, gain = 0, res_val;
int ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA;
@ -264,6 +320,48 @@ static void wcd_clsh_set_hph_mode(struct snd_soc_component *comp,
ipeak);
}
static void wcd_clsh_v3_set_hph_mode(struct snd_soc_component *component,
int mode)
{
u8 val;
switch (mode) {
case CLS_H_NORMAL:
val = 0x00;
break;
case CLS_AB:
case CLS_H_ULP:
val = 0x0C;
break;
case CLS_AB_HIFI:
case CLS_H_HIFI:
val = 0x08;
break;
case CLS_H_LP:
case CLS_H_LOHIFI:
case CLS_AB_LP:
case CLS_AB_LOHIFI:
val = 0x04;
break;
default:
dev_err(component->dev, "%s:Invalid mode %d\n", __func__, mode);
return;
}
snd_soc_component_update_bits(component, WCD9XXX_ANA_HPH, 0x0C, val);
}
void wcd_clsh_set_hph_mode(struct wcd_clsh_ctrl *ctrl, int mode)
{
struct snd_soc_component *comp = ctrl->comp;
if (ctrl->codec_version >= WCD937X)
wcd_clsh_v3_set_hph_mode(comp, mode);
else
wcd_clsh_v2_set_hph_mode(comp, mode);
}
static void wcd_clsh_set_flyback_current(struct snd_soc_component *comp,
int mode)
{
@ -289,6 +387,130 @@ static void wcd_clsh_set_buck_regulator_mode(struct snd_soc_component *comp,
WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_H);
}
static void wcd_clsh_v3_set_buck_regulator_mode(struct snd_soc_component *component,
int mode)
{
snd_soc_component_update_bits(component, WCD9XXX_ANA_RX_SUPPLIES,
0x02, 0x00);
}
static void wcd_clsh_v3_set_flyback_mode(struct snd_soc_component *component,
int mode)
{
if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI ||
mode == CLS_AB_HIFI || mode == CLS_AB_LOHIFI) {
snd_soc_component_update_bits(component,
WCD9XXX_ANA_RX_SUPPLIES,
0x04, 0x04);
snd_soc_component_update_bits(component,
WCD9XXX_FLYBACK_VNEG_CTRL_4,
0xF0, 0x80);
} else {
snd_soc_component_update_bits(component,
WCD9XXX_ANA_RX_SUPPLIES,
0x04, 0x00); /* set to Default */
snd_soc_component_update_bits(component,
WCD9XXX_FLYBACK_VNEG_CTRL_4,
0xF0, 0x70);
}
}
static void wcd_clsh_v3_force_iq_ctl(struct snd_soc_component *component,
int mode, bool enable)
{
if (enable) {
snd_soc_component_update_bits(component,
WCD9XXX_FLYBACK_VNEGDAC_CTRL_2,
0xE0, 0xA0);
/* 100usec delay is needed as per HW requirement */
usleep_range(100, 110);
snd_soc_component_update_bits(component,
WCD9XXX_CLASSH_MODE_3,
0x02, 0x02);
snd_soc_component_update_bits(component,
WCD9XXX_CLASSH_MODE_2,
0xFF, 0x1C);
if (mode == CLS_H_LOHIFI || mode == CLS_AB_LOHIFI) {
snd_soc_component_update_bits(component,
WCD9XXX_HPH_NEW_INT_PA_MISC2,
0x20, 0x20);
snd_soc_component_update_bits(component,
WCD9XXX_RX_BIAS_HPH_LOWPOWER,
0xF0, 0xC0);
snd_soc_component_update_bits(component,
WCD9XXX_HPH_PA_CTL1,
0x0E, 0x02);
}
} else {
snd_soc_component_update_bits(component,
WCD9XXX_HPH_NEW_INT_PA_MISC2,
0x20, 0x00);
snd_soc_component_update_bits(component,
WCD9XXX_RX_BIAS_HPH_LOWPOWER,
0xF0, 0x80);
snd_soc_component_update_bits(component,
WCD9XXX_HPH_PA_CTL1,
0x0E, 0x06);
}
}
static void wcd_clsh_v3_flyback_ctrl(struct snd_soc_component *component,
struct wcd_clsh_ctrl *ctrl,
int mode,
bool enable)
{
/* enable/disable flyback */
if ((enable && (++ctrl->flyback_users == 1)) ||
(!enable && (--ctrl->flyback_users == 0))) {
snd_soc_component_update_bits(component,
WCD9XXX_FLYBACK_VNEG_CTRL_1,
0xE0, 0xE0);
snd_soc_component_update_bits(component,
WCD9XXX_ANA_RX_SUPPLIES,
(1 << 6), (enable << 6));
/*
* 100us sleep is required after flyback enable/disable
* as per HW requirement
*/
usleep_range(100, 110);
snd_soc_component_update_bits(component,
WCD9XXX_FLYBACK_VNEGDAC_CTRL_2,
0xE0, 0xE0);
/* 500usec delay is needed as per HW requirement */
usleep_range(500, 500 + WCD_USLEEP_RANGE);
}
}
static void wcd_clsh_v3_set_flyback_current(struct snd_soc_component *component,
int mode)
{
snd_soc_component_update_bits(component, WCD9XXX_V3_RX_BIAS_FLYB_BUFF,
0x0F, 0x0A);
snd_soc_component_update_bits(component, WCD9XXX_V3_RX_BIAS_FLYB_BUFF,
0xF0, 0xA0);
/* Sleep needed to avoid click and pop as per HW requirement */
usleep_range(100, 110);
}
static void wcd_clsh_v3_state_aux(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
struct snd_soc_component *component = ctrl->comp;
if (is_enable) {
wcd_clsh_v3_set_buck_mode(component, mode);
wcd_clsh_v3_set_flyback_mode(component, mode);
wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_flyback_current(component, mode);
wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true);
} else {
wcd_clsh_v3_buck_ctrl(component, ctrl, mode, false);
wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, false);
wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL);
wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL);
}
}
static void wcd_clsh_state_lo(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
@ -316,6 +538,38 @@ static void wcd_clsh_state_lo(struct wcd_clsh_ctrl *ctrl, int req_state,
}
}
static void wcd_clsh_v3_state_hph_r(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
struct snd_soc_component *component = ctrl->comp;
if (mode == CLS_H_NORMAL) {
dev_dbg(component->dev, "%s: Normal mode not applicable for hph_r\n",
__func__);
return;
}
if (is_enable) {
wcd_clsh_v3_set_buck_regulator_mode(component, mode);
wcd_clsh_v3_set_flyback_mode(component, mode);
wcd_clsh_v3_force_iq_ctl(component, mode, true);
wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_flyback_current(component, mode);
wcd_clsh_v3_set_buck_mode(component, mode);
wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_hph_mode(component, mode);
} else {
wcd_clsh_v3_set_hph_mode(component, CLS_H_NORMAL);
/* buck and flyback set to default mode and disable */
wcd_clsh_v3_flyback_ctrl(component, ctrl, CLS_H_NORMAL, false);
wcd_clsh_v3_buck_ctrl(component, ctrl, CLS_H_NORMAL, false);
wcd_clsh_v3_force_iq_ctl(component, CLS_H_NORMAL, false);
wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL);
wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL);
}
}
static void wcd_clsh_state_hph_r(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
@ -353,10 +607,10 @@ static void wcd_clsh_state_hph_r(struct wcd_clsh_ctrl *ctrl, int req_state,
wcd_clsh_set_flyback_current(comp, mode);
wcd_clsh_set_buck_mode(comp, mode);
wcd_clsh_buck_ctrl(ctrl, mode, true);
wcd_clsh_set_hph_mode(comp, mode);
wcd_clsh_v2_set_hph_mode(comp, mode);
wcd_clsh_set_gain_path(ctrl, mode);
} else {
wcd_clsh_set_hph_mode(comp, CLS_H_NORMAL);
wcd_clsh_v2_set_hph_mode(comp, CLS_H_NORMAL);
if (mode != CLS_AB) {
snd_soc_component_update_bits(comp,
@ -374,6 +628,38 @@ static void wcd_clsh_state_hph_r(struct wcd_clsh_ctrl *ctrl, int req_state,
}
}
static void wcd_clsh_v3_state_hph_l(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
struct snd_soc_component *component = ctrl->comp;
if (mode == CLS_H_NORMAL) {
dev_dbg(component->dev, "%s: Normal mode not applicable for hph_l\n",
__func__);
return;
}
if (is_enable) {
wcd_clsh_v3_set_buck_regulator_mode(component, mode);
wcd_clsh_v3_set_flyback_mode(component, mode);
wcd_clsh_v3_force_iq_ctl(component, mode, true);
wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_flyback_current(component, mode);
wcd_clsh_v3_set_buck_mode(component, mode);
wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_hph_mode(component, mode);
} else {
wcd_clsh_v3_set_hph_mode(component, CLS_H_NORMAL);
/* set buck and flyback to Default Mode */
wcd_clsh_v3_flyback_ctrl(component, ctrl, CLS_H_NORMAL, false);
wcd_clsh_v3_buck_ctrl(component, ctrl, CLS_H_NORMAL, false);
wcd_clsh_v3_force_iq_ctl(component, CLS_H_NORMAL, false);
wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL);
wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL);
}
}
static void wcd_clsh_state_hph_l(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
@ -411,10 +697,10 @@ static void wcd_clsh_state_hph_l(struct wcd_clsh_ctrl *ctrl, int req_state,
wcd_clsh_set_flyback_current(comp, mode);
wcd_clsh_set_buck_mode(comp, mode);
wcd_clsh_buck_ctrl(ctrl, mode, true);
wcd_clsh_set_hph_mode(comp, mode);
wcd_clsh_v2_set_hph_mode(comp, mode);
wcd_clsh_set_gain_path(ctrl, mode);
} else {
wcd_clsh_set_hph_mode(comp, CLS_H_NORMAL);
wcd_clsh_v2_set_hph_mode(comp, CLS_H_NORMAL);
if (mode != CLS_AB) {
snd_soc_component_update_bits(comp,
@ -432,6 +718,32 @@ static void wcd_clsh_state_hph_l(struct wcd_clsh_ctrl *ctrl, int req_state,
}
}
static void wcd_clsh_v3_state_ear(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
struct snd_soc_component *component = ctrl->comp;
if (is_enable) {
wcd_clsh_v3_set_buck_regulator_mode(component, mode);
wcd_clsh_v3_set_flyback_mode(component, mode);
wcd_clsh_v3_force_iq_ctl(component, mode, true);
wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_flyback_current(component, mode);
wcd_clsh_v3_set_buck_mode(component, mode);
wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_hph_mode(component, mode);
} else {
wcd_clsh_v3_set_hph_mode(component, CLS_H_NORMAL);
/* set buck and flyback to Default Mode */
wcd_clsh_v3_flyback_ctrl(component, ctrl, CLS_H_NORMAL, false);
wcd_clsh_v3_buck_ctrl(component, ctrl, CLS_H_NORMAL, false);
wcd_clsh_v3_force_iq_ctl(component, CLS_H_NORMAL, false);
wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL);
wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL);
}
}
static void wcd_clsh_state_ear(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
@ -472,16 +784,30 @@ static int _wcd_clsh_ctrl_set_state(struct wcd_clsh_ctrl *ctrl, int req_state,
{
switch (req_state) {
case WCD_CLSH_STATE_EAR:
wcd_clsh_state_ear(ctrl, req_state, is_enable, mode);
if (ctrl->codec_version >= WCD937X)
wcd_clsh_v3_state_ear(ctrl, req_state, is_enable, mode);
else
wcd_clsh_state_ear(ctrl, req_state, is_enable, mode);
break;
case WCD_CLSH_STATE_HPHL:
wcd_clsh_state_hph_l(ctrl, req_state, is_enable, mode);
if (ctrl->codec_version >= WCD937X)
wcd_clsh_v3_state_hph_l(ctrl, req_state, is_enable, mode);
else
wcd_clsh_state_hph_l(ctrl, req_state, is_enable, mode);
break;
case WCD_CLSH_STATE_HPHR:
wcd_clsh_state_hph_r(ctrl, req_state, is_enable, mode);
if (ctrl->codec_version >= WCD937X)
wcd_clsh_v3_state_hph_r(ctrl, req_state, is_enable, mode);
else
wcd_clsh_state_hph_r(ctrl, req_state, is_enable, mode);
break;
case WCD_CLSH_STATE_LO:
wcd_clsh_state_lo(ctrl, req_state, is_enable, mode);
if (ctrl->codec_version < WCD937X)
wcd_clsh_state_lo(ctrl, req_state, is_enable, mode);
break;
case WCD_CLSH_STATE_AUX:
if (ctrl->codec_version >= WCD937X)
wcd_clsh_v3_state_aux(ctrl, req_state, is_enable, mode);
break;
default:
break;
@ -504,6 +830,7 @@ static bool wcd_clsh_is_state_valid(int state)
case WCD_CLSH_STATE_HPHL:
case WCD_CLSH_STATE_HPHR:
case WCD_CLSH_STATE_LO:
case WCD_CLSH_STATE_AUX:
return true;
default:
return false;
@ -565,6 +892,7 @@ struct wcd_clsh_ctrl *wcd_clsh_ctrl_alloc(struct snd_soc_component *comp,
ctrl->state = WCD_CLSH_STATE_IDLE;
ctrl->comp = comp;
ctrl->codec_version = version;
return ctrl;
}

16
sound/soc/codecs/wcd-clsh-v2.h
View File

@ -22,8 +22,11 @@ enum wcd_clsh_event {
#define WCD_CLSH_STATE_HPHL BIT(1)
#define WCD_CLSH_STATE_HPHR BIT(2)
#define WCD_CLSH_STATE_LO BIT(3)
#define WCD_CLSH_STATE_AUX BIT(4)
#define WCD_CLSH_STATE_MAX 4
#define WCD_CLSH_V3_STATE_MAX 5
#define NUM_CLSH_STATES_V2 BIT(WCD_CLSH_STATE_MAX)
#define NUM_CLSH_STATES_V3 BIT(WCD_CLSH_V3_STATE_MAX)
enum wcd_clsh_mode {
CLS_H_NORMAL = 0, /* Class-H Default */
@ -31,9 +34,20 @@ enum wcd_clsh_mode {
CLS_H_LP, /* Class-H Low Power */
CLS_AB, /* Class-AB */
CLS_H_LOHIFI, /* LoHIFI */
CLS_H_ULP, /* Ultra Low power */
CLS_AB_HIFI, /* Class-AB */
CLS_AB_LP, /* Class-AB Low Power */
CLS_AB_LOHIFI, /* Class-AB Low HIFI */
CLS_NONE, /* None of the above modes */
};
enum wcd_codec_version {
WCD9335 = 0,
WCD934X = 1,
/* New CLSH after this */
WCD937X = 2,
WCD938X = 3,
};
struct wcd_clsh_ctrl;
extern struct wcd_clsh_ctrl *wcd_clsh_ctrl_alloc(
@ -45,5 +59,7 @@ extern int wcd_clsh_ctrl_set_state(struct wcd_clsh_ctrl *ctrl,
enum wcd_clsh_event clsh_event,
int nstate,
enum wcd_clsh_mode mode);
extern void wcd_clsh_set_hph_mode(struct wcd_clsh_ctrl *ctrl,
int mode);
#endif /* _WCD_CLSH_V2_H_ */

315
sound/soc/codecs/wcd938x-sdw.c Normal file
View File

@ -0,0 +1,315 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021, Linaro Limited
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/component.h>
#include <sound/soc.h>
#include <linux/pm_runtime.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_type.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include "wcd938x.h"
#define SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(m) (0xE0 + 0x10 * (m))
static struct wcd938x_sdw_ch_info wcd938x_sdw_rx_ch_info[] = {
WCD_SDW_CH(WCD938X_HPH_L, WCD938X_HPH_PORT, BIT(0)),
WCD_SDW_CH(WCD938X_HPH_R, WCD938X_HPH_PORT, BIT(1)),
WCD_SDW_CH(WCD938X_CLSH, WCD938X_CLSH_PORT, BIT(0)),
WCD_SDW_CH(WCD938X_COMP_L, WCD938X_COMP_PORT, BIT(0)),
WCD_SDW_CH(WCD938X_COMP_R, WCD938X_COMP_PORT, BIT(1)),
WCD_SDW_CH(WCD938X_LO, WCD938X_LO_PORT, BIT(0)),
WCD_SDW_CH(WCD938X_DSD_L, WCD938X_DSD_PORT, BIT(0)),
WCD_SDW_CH(WCD938X_DSD_R, WCD938X_DSD_PORT, BIT(1)),
};
static struct wcd938x_sdw_ch_info wcd938x_sdw_tx_ch_info[] = {
WCD_SDW_CH(WCD938X_ADC1, WCD938X_ADC_1_2_PORT, BIT(0)),
WCD_SDW_CH(WCD938X_ADC2, WCD938X_ADC_1_2_PORT, BIT(1)),
WCD_SDW_CH(WCD938X_ADC3, WCD938X_ADC_3_4_PORT, BIT(0)),
WCD_SDW_CH(WCD938X_ADC4, WCD938X_ADC_3_4_PORT, BIT(1)),
WCD_SDW_CH(WCD938X_DMIC0, WCD938X_DMIC_0_3_MBHC_PORT, BIT(0)),
WCD_SDW_CH(WCD938X_DMIC1, WCD938X_DMIC_0_3_MBHC_PORT, BIT(1)),
WCD_SDW_CH(WCD938X_MBHC, WCD938X_DMIC_0_3_MBHC_PORT, BIT(2)),
WCD_SDW_CH(WCD938X_DMIC2, WCD938X_DMIC_0_3_MBHC_PORT, BIT(2)),
WCD_SDW_CH(WCD938X_DMIC3, WCD938X_DMIC_0_3_MBHC_PORT, BIT(3)),
WCD_SDW_CH(WCD938X_DMIC4, WCD938X_DMIC_4_7_PORT, BIT(0)),
WCD_SDW_CH(WCD938X_DMIC5, WCD938X_DMIC_4_7_PORT, BIT(1)),
WCD_SDW_CH(WCD938X_DMIC6, WCD938X_DMIC_4_7_PORT, BIT(2)),
WCD_SDW_CH(WCD938X_DMIC7, WCD938X_DMIC_4_7_PORT, BIT(3)),
};
static struct sdw_dpn_prop wcd938x_dpn_prop[WCD938X_MAX_SWR_PORTS] = {
{
.num = 1,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 8,
.simple_ch_prep_sm = true,
}, {
.num = 2,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 4,
.simple_ch_prep_sm = true,
}, {
.num = 3,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 4,
.simple_ch_prep_sm = true,
}, {
.num = 4,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 4,
.simple_ch_prep_sm = true,
}, {
.num = 5,
.type = SDW_DPN_SIMPLE,
.min_ch = 1,
.max_ch = 4,
.simple_ch_prep_sm = true,
}
};
struct device *wcd938x_sdw_device_get(struct device_node *np)
{
return bus_find_device_by_of_node(&sdw_bus_type, np);
}
EXPORT_SYMBOL_GPL(wcd938x_sdw_device_get);
int wcd938x_swr_get_current_bank(struct sdw_slave *sdev)
{
int bank;
bank = sdw_read(sdev, SDW_SCP_CTRL);
return ((bank & 0x40) ? 1 : 0);
}
EXPORT_SYMBOL_GPL(wcd938x_swr_get_current_bank);
int wcd938x_sdw_hw_params(struct wcd938x_sdw_priv *wcd,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct sdw_port_config port_config[WCD938X_MAX_SWR_PORTS];
unsigned long ch_mask;
int i, j;
wcd->sconfig.ch_count = 1;
wcd->active_ports = 0;
for (i = 0; i < WCD938X_MAX_SWR_PORTS; i++) {
ch_mask = wcd->port_config[i].ch_mask;
if (!ch_mask)
continue;
for_each_set_bit(j, &ch_mask, 4)
wcd->sconfig.ch_count++;
port_config[wcd->active_ports] = wcd->port_config[i];
wcd->active_ports++;
}
wcd->sconfig.bps = 1;
wcd->sconfig.frame_rate = params_rate(params);
if (wcd->is_tx)
wcd->sconfig.direction = SDW_DATA_DIR_TX;
else
wcd->sconfig.direction = SDW_DATA_DIR_RX;
wcd->sconfig.type = SDW_STREAM_PCM;
return sdw_stream_add_slave(wcd->sdev, &wcd->sconfig,
&port_config[0], wcd->active_ports,
wcd->sruntime);
}
EXPORT_SYMBOL_GPL(wcd938x_sdw_hw_params);
int wcd938x_sdw_free(struct wcd938x_sdw_priv *wcd,
struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
sdw_stream_remove_slave(wcd->sdev, wcd->sruntime);
return 0;
}
EXPORT_SYMBOL_GPL(wcd938x_sdw_free);
int wcd938x_sdw_set_sdw_stream(struct wcd938x_sdw_priv *wcd,
struct snd_soc_dai *dai,
void *stream, int direction)
{
wcd->sruntime = stream;
return 0;
}
EXPORT_SYMBOL_GPL(wcd938x_sdw_set_sdw_stream);
static int wcd9380_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
return 0;
}
static int wcd9380_bus_config(struct sdw_slave *slave,
struct sdw_bus_params *params)
{
sdw_write(slave, SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(params->next_bank), 0x01);
return 0;
}
static int wcd9380_interrupt_callback(struct sdw_slave *slave,
struct sdw_slave_intr_status *status)
{
struct wcd938x_sdw_priv *wcd = dev_get_drvdata(&slave->dev);
return wcd938x_handle_sdw_irq(wcd);
}
static struct sdw_slave_ops wcd9380_slave_ops = {
.update_status = wcd9380_update_status,
.interrupt_callback = wcd9380_interrupt_callback,
.bus_config = wcd9380_bus_config,
};
static int wcd938x_sdw_component_bind(struct device *dev,
struct device *master, void *data)
{
return 0;
}
static void wcd938x_sdw_component_unbind(struct device *dev,
struct device *master, void *data)
{
}
static const struct component_ops wcd938x_sdw_component_ops = {
.bind = wcd938x_sdw_component_bind,
.unbind = wcd938x_sdw_component_unbind,
};
static int wcd9380_probe(struct sdw_slave *pdev,
const struct sdw_device_id *id)
{
struct device *dev = &pdev->dev;
struct wcd938x_sdw_priv *wcd;
int ret;
wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL);
if (!wcd)
return -ENOMEM;
/**
* Port map index starts with 0, however the data port for this codec
* are from index 1
*/
if (of_property_read_bool(dev->of_node, "qcom,tx-port-mapping")) {
wcd->is_tx = true;
ret = of_property_read_u32_array(dev->of_node, "qcom,tx-port-mapping",
&pdev->m_port_map[1],
WCD938X_MAX_TX_SWR_PORTS);
} else {
ret = of_property_read_u32_array(dev->of_node, "qcom,rx-port-mapping",
&pdev->m_port_map[1],
WCD938X_MAX_SWR_PORTS);
}
if (ret < 0)
dev_info(dev, "Static Port mapping not specified\n");
wcd->sdev = pdev;
dev_set_drvdata(dev, wcd);
pdev->prop.scp_int1_mask = SDW_SCP_INT1_IMPL_DEF |
SDW_SCP_INT1_BUS_CLASH |
SDW_SCP_INT1_PARITY;
pdev->prop.lane_control_support = true;
if (wcd->is_tx) {
struct regmap *rm;
pdev->prop.source_ports = GENMASK(WCD938X_MAX_SWR_PORTS, 0);
pdev->prop.src_dpn_prop = wcd938x_dpn_prop;
wcd->ch_info = &wcd938x_sdw_tx_ch_info[0];
pdev->prop.wake_capable = true;
rm = devm_regmap_init_sdw(pdev, &wcd938x_regmap_config);
if (IS_ERR(rm))
return PTR_ERR(rm);
} else {
pdev->prop.sink_ports = GENMASK(WCD938X_MAX_SWR_PORTS, 0);
pdev->prop.sink_dpn_prop = wcd938x_dpn_prop;
wcd->ch_info = &wcd938x_sdw_rx_ch_info[0];
}
pm_runtime_set_autosuspend_delay(dev, 3000);
pm_runtime_use_autosuspend(dev);
pm_runtime_mark_last_busy(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
return component_add(dev, &wcd938x_sdw_component_ops);
}
static const struct sdw_device_id wcd9380_slave_id[] = {
SDW_SLAVE_ENTRY(0x0217, 0x10d, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, wcd9380_slave_id);
static int __maybe_unused wcd938x_sdw_runtime_suspend(struct device *dev)
{
struct regmap *regmap = dev_get_regmap(dev, NULL);
if (regmap) {
regcache_cache_only(regmap, true);
regcache_mark_dirty(regmap);
}
return 0;
}
static int __maybe_unused wcd938x_sdw_runtime_resume(struct device *dev)
{
struct regmap *regmap = dev_get_regmap(dev, NULL);
if (regmap) {
regcache_cache_only(regmap, false);
regcache_sync(regmap);
}
pm_runtime_mark_last_busy(dev);
return 0;
}
static const struct dev_pm_ops wcd938x_sdw_pm_ops = {
SET_RUNTIME_PM_OPS(wcd938x_sdw_runtime_suspend, wcd938x_sdw_runtime_resume, NULL)
};
static struct sdw_driver wcd9380_codec_driver = {
.probe = wcd9380_probe,
.ops = &wcd9380_slave_ops,
.id_table = wcd9380_slave_id,
.driver = {
.name = "wcd9380-codec",
.pm = &wcd938x_sdw_pm_ops,
}
};
module_sdw_driver(wcd9380_codec_driver);
MODULE_DESCRIPTION("WCD938X SDW codec driver");
MODULE_LICENSE("GPL");

3753
sound/soc/codecs/wcd938x.c Normal file
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File diff suppressed because it is too large Load Diff

720
sound/soc/codecs/wcd938x.h Normal file
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@ -0,0 +1,720 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __WCD938X_H__
#define __WCD938X_H__
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_type.h>
#define WCD938X_BASE_ADDRESS (0x3000)
#define WCD938X_ANA_PAGE_REGISTER (0x3000)
#define WCD938X_ANA_BIAS (0x3001)
#define WCD938X_ANA_RX_SUPPLIES (0x3008)
#define WCD938X_RX_BIAS_EN_MASK BIT(0)
#define WCD938X_REGULATOR_MODE_MASK BIT(1)
#define WCD938X_REGULATOR_MODE_CLASS_AB 1
#define WCD938X_VNEG_EN_MASK BIT(6)
#define WCD938X_VPOS_EN_MASK BIT(7)
#define WCD938X_ANA_HPH (0x3009)
#define WCD938X_HPHR_REF_EN_MASK BIT(4)
#define WCD938X_HPHL_REF_EN_MASK BIT(5)
#define WCD938X_HPHR_EN_MASK BIT(6)
#define WCD938X_HPHL_EN_MASK BIT(7)
#define WCD938X_ANA_EAR (0x300A)
#define WCD938X_ANA_EAR_COMPANDER_CTL (0x300B)
#define WCD938X_GAIN_OVRD_REG_MASK BIT(7)
#define WCD938X_EAR_GAIN_MASK GENMASK(6, 2)
#define WCD938X_ANA_TX_CH1 (0x300E)
#define WCD938X_ANA_TX_CH2 (0x300F)
#define WCD938X_HPF1_INIT_MASK BIT(6)
#define WCD938X_HPF2_INIT_MASK BIT(5)
#define WCD938X_ANA_TX_CH3 (0x3010)
#define WCD938X_ANA_TX_CH4 (0x3011)
#define WCD938X_HPF3_INIT_MASK BIT(6)
#define WCD938X_HPF4_INIT_MASK BIT(5)
#define WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC (0x3012)
#define WCD938X_ANA_MICB3_DSP_EN_LOGIC (0x3013)
#define WCD938X_ANA_MBHC_MECH (0x3014)
#define WCD938X_MBHC_L_DET_EN_MASK BIT(7)
#define WCD938X_MBHC_L_DET_EN BIT(7)
#define WCD938X_MBHC_GND_DET_EN_MASK BIT(6)
#define WCD938X_MBHC_MECH_DETECT_TYPE_MASK BIT(5)
#define WCD938X_MBHC_MECH_DETECT_TYPE_INS 1
#define WCD938X_MBHC_HPHL_PLUG_TYPE_MASK BIT(4)
#define WCD938X_MBHC_HPHL_PLUG_TYPE_NO 1
#define WCD938X_MBHC_GND_PLUG_TYPE_MASK BIT(3)
#define WCD938X_MBHC_GND_PLUG_TYPE_NO 1
#define WCD938X_MBHC_HSL_PULLUP_COMP_EN BIT(2)
#define WCD938X_MBHC_HSG_PULLUP_COMP_EN BIT(1)
#define WCD938X_MBHC_HPHL_100K_TO_GND_EN BIT(0)
#define WCD938X_ANA_MBHC_ELECT (0x3015)
#define WCD938X_ANA_MBHC_BD_ISRC_CTL_MASK GENMASK(6, 4)
#define WCD938X_ANA_MBHC_BD_ISRC_100UA GENMASK(5, 4)
#define WCD938X_ANA_MBHC_BD_ISRC_OFF 0
#define WCD938X_ANA_MBHC_BIAS_EN_MASK BIT(0)
#define WCD938X_ANA_MBHC_BIAS_EN BIT(0)
#define WCD938X_ANA_MBHC_ZDET (0x3016)
#define WCD938X_ANA_MBHC_RESULT_1 (0x3017)
#define WCD938X_ANA_MBHC_RESULT_2 (0x3018)
#define WCD938X_ANA_MBHC_RESULT_3 (0x3019)
#define WCD938X_MBHC_BTN_RESULT_MASK GENMASK(2, 0)
#define WCD938X_ANA_MBHC_BTN0 (0x301A)
#define WCD938X_MBHC_BTN_VTH_MASK GENMASK(7, 2)
#define WCD938X_ANA_MBHC_BTN1 (0x301B)
#define WCD938X_ANA_MBHC_BTN2 (0x301C)
#define WCD938X_ANA_MBHC_BTN3 (0x301D)
#define WCD938X_ANA_MBHC_BTN4 (0x301E)
#define WCD938X_ANA_MBHC_BTN5 (0x301F)
#define WCD938X_VTH_MASK GENMASK(7, 2)
#define WCD938X_ANA_MBHC_BTN6 (0x3020)
#define WCD938X_ANA_MBHC_BTN7 (0x3021)
#define WCD938X_ANA_MICB1 (0x3022)
#define WCD938X_MICB_VOUT_MASK GENMASK(5, 0)
#define WCD938X_MICB_EN_MASK GENMASK(7, 6)
#define WCD938X_MICB_DISABLE 0
#define WCD938X_MICB_ENABLE 1
#define WCD938X_MICB_PULL_UP 2
#define WCD938X_MICB_PULL_DOWN 3
#define WCD938X_ANA_MICB2 (0x3023)
#define WCD938X_ANA_MICB2_ENABLE BIT(6)
#define WCD938X_ANA_MICB2_ENABLE_MASK GENMASK(7, 6)
#define WCD938X_ANA_MICB2_VOUT_MASK GENMASK(5, 0)
#define WCD938X_ANA_MICB2_RAMP (0x3024)
#define WCD938X_RAMP_EN_MASK BIT(7)
#define WCD938X_RAMP_SHIFT_CTRL_MASK GENMASK(4, 2)
#define WCD938X_ANA_MICB3 (0x3025)
#define WCD938X_ANA_MICB4 (0x3026)
#define WCD938X_BIAS_CTL (0x3028)
#define WCD938X_BIAS_VBG_FINE_ADJ (0x3029)
#define WCD938X_LDOL_VDDCX_ADJUST (0x3040)
#define WCD938X_LDOL_DISABLE_LDOL (0x3041)
#define WCD938X_MBHC_CTL_CLK (0x3056)
#define WCD938X_MBHC_CTL_ANA (0x3057)
#define WCD938X_MBHC_CTL_SPARE_1 (0x3058)
#define WCD938X_MBHC_CTL_SPARE_2 (0x3059)
#define WCD938X_MBHC_CTL_BCS (0x305A)
#define WCD938X_MBHC_MOISTURE_DET_FSM_STATUS (0x305B)
#define WCD938X_MBHC_TEST_CTL (0x305C)
#define WCD938X_LDOH_MODE (0x3067)
#define WCD938X_LDOH_EN_MASK BIT(7)
#define WCD938X_LDOH_BIAS (0x3068)
#define WCD938X_LDOH_STB_LOADS (0x3069)
#define WCD938X_LDOH_SLOWRAMP (0x306A)
#define WCD938X_MICB1_TEST_CTL_1 (0x306B)
#define WCD938X_MICB1_TEST_CTL_2 (0x306C)
#define WCD938X_MICB1_TEST_CTL_3 (0x306D)
#define WCD938X_MICB2_TEST_CTL_1 (0x306E)
#define WCD938X_MICB2_TEST_CTL_2 (0x306F)
#define WCD938X_MICB2_TEST_CTL_3 (0x3070)
#define WCD938X_MICB3_TEST_CTL_1 (0x3071)
#define WCD938X_MICB3_TEST_CTL_2 (0x3072)
#define WCD938X_MICB3_TEST_CTL_3 (0x3073)
#define WCD938X_MICB4_TEST_CTL_1 (0x3074)
#define WCD938X_MICB4_TEST_CTL_2 (0x3075)
#define WCD938X_MICB4_TEST_CTL_3 (0x3076)
#define WCD938X_TX_COM_ADC_VCM (0x3077)
#define WCD938X_TX_COM_BIAS_ATEST (0x3078)
#define WCD938X_TX_COM_SPARE1 (0x3079)
#define WCD938X_TX_COM_SPARE2 (0x307A)
#define WCD938X_TX_COM_TXFE_DIV_CTL (0x307B)
#define WCD938X_TX_COM_TXFE_DIV_START (0x307C)
#define WCD938X_TX_COM_SPARE3 (0x307D)
#define WCD938X_TX_COM_SPARE4 (0x307E)
#define WCD938X_TX_1_2_TEST_EN (0x307F)
#define WCD938X_TX_1_2_ADC_IB (0x3080)
#define WCD938X_TX_1_2_ATEST_REFCTL (0x3081)
#define WCD938X_TX_1_2_TEST_CTL (0x3082)
#define WCD938X_TX_1_2_TEST_BLK_EN1 (0x3083)
#define WCD938X_TX_1_2_TXFE1_CLKDIV (0x3084)
#define WCD938X_TX_1_2_SAR2_ERR (0x3085)
#define WCD938X_TX_1_2_SAR1_ERR (0x3086)
#define WCD938X_TX_3_4_TEST_EN (0x3087)
#define WCD938X_TX_3_4_ADC_IB (0x3088)
#define WCD938X_TX_3_4_ATEST_REFCTL (0x3089)
#define WCD938X_TX_3_4_TEST_CTL (0x308A)
#define WCD938X_TX_3_4_TEST_BLK_EN3 (0x308B)
#define WCD938X_TX_3_4_TXFE3_CLKDIV (0x308C)
#define WCD938X_TX_3_4_SAR4_ERR (0x308D)
#define WCD938X_TX_3_4_SAR3_ERR (0x308E)
#define WCD938X_TX_3_4_TEST_BLK_EN2 (0x308F)
#define WCD938X_TX_3_4_TXFE2_CLKDIV (0x3090)
#define WCD938X_TX_3_4_SPARE1 (0x3091)
#define WCD938X_TX_3_4_TEST_BLK_EN4 (0x3092)
#define WCD938X_TX_3_4_TXFE4_CLKDIV (0x3093)
#define WCD938X_TX_3_4_SPARE2 (0x3094)
#define WCD938X_CLASSH_MODE_1 (0x3097)
#define WCD938X_CLASSH_MODE_2 (0x3098)
#define WCD938X_CLASSH_MODE_3 (0x3099)
#define WCD938X_CLASSH_CTRL_VCL_1 (0x309A)
#define WCD938X_CLASSH_CTRL_VCL_2 (0x309B)
#define WCD938X_CLASSH_CTRL_CCL_1 (0x309C)
#define WCD938X_CLASSH_CTRL_CCL_2 (0x309D)
#define WCD938X_CLASSH_CTRL_CCL_3 (0x309E)
#define WCD938X_CLASSH_CTRL_CCL_4 (0x309F)
#define WCD938X_CLASSH_CTRL_CCL_5 (0x30A0)
#define WCD938X_CLASSH_BUCK_TMUX_A_D (0x30A1)
#define WCD938X_CLASSH_BUCK_SW_DRV_CNTL (0x30A2)
#define WCD938X_CLASSH_SPARE (0x30A3)
#define WCD938X_FLYBACK_EN (0x30A4)
#define WCD938X_EN_CUR_DET_MASK BIT(2)
#define WCD938X_FLYBACK_VNEG_CTRL_1 (0x30A5)
#define WCD938X_FLYBACK_VNEG_CTRL_2 (0x30A6)
#define WCD938X_FLYBACK_VNEG_CTRL_3 (0x30A7)
#define WCD938X_FLYBACK_VNEG_CTRL_4 (0x30A8)
#define WCD938X_FLYBACK_VNEG_CTRL_5 (0x30A9)
#define WCD938X_FLYBACK_VNEG_CTRL_6 (0x30AA)
#define WCD938X_FLYBACK_VNEG_CTRL_7 (0x30AB)
#define WCD938X_FLYBACK_VNEG_CTRL_8 (0x30AC)
#define WCD938X_FLYBACK_VNEG_CTRL_9 (0x30AD)
#define WCD938X_FLYBACK_VNEGDAC_CTRL_1 (0x30AE)
#define WCD938X_FLYBACK_VNEGDAC_CTRL_2 (0x30AF)
#define WCD938X_FLYBACK_VNEGDAC_CTRL_3 (0x30B0)
#define WCD938X_FLYBACK_CTRL_1 (0x30B1)
#define WCD938X_FLYBACK_TEST_CTL (0x30B2)
#define WCD938X_RX_AUX_SW_CTL (0x30B3)
#define WCD938X_RX_PA_AUX_IN_CONN (0x30B4)
#define WCD938X_RX_TIMER_DIV (0x30B5)
#define WCD938X_RX_OCP_CTL (0x30B6)
#define WCD938X_RX_OCP_COUNT (0x30B7)
#define WCD938X_RX_BIAS_EAR_DAC (0x30B8)
#define WCD938X_RX_BIAS_EAR_AMP (0x30B9)
#define WCD938X_RX_BIAS_HPH_LDO (0x30BA)
#define WCD938X_RX_BIAS_HPH_PA (0x30BB)
#define WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2 (0x30BC)
#define WCD938X_RX_BIAS_HPH_RDAC_LDO (0x30BD)
#define WCD938X_RX_BIAS_HPH_CNP1 (0x30BE)
#define WCD938X_RX_BIAS_HPH_LOWPOWER (0x30BF)
#define WCD938X_RX_BIAS_AUX_DAC (0x30C0)
#define WCD938X_RX_BIAS_AUX_AMP (0x30C1)
#define WCD938X_RX_BIAS_VNEGDAC_BLEEDER (0x30C2)
#define WCD938X_RX_BIAS_MISC (0x30C3)
#define WCD938X_RX_BIAS_BUCK_RST (0x30C4)
#define WCD938X_RX_BIAS_BUCK_VREF_ERRAMP (0x30C5)
#define WCD938X_RX_BIAS_FLYB_ERRAMP (0x30C6)
#define WCD938X_RX_BIAS_FLYB_BUFF (0x30C7)
#define WCD938X_RX_BIAS_FLYB_MID_RST (0x30C8)
#define WCD938X_HPH_L_STATUS (0x30C9)
#define WCD938X_HPH_R_STATUS (0x30CA)
#define WCD938X_HPH_CNP_EN (0x30CB)
#define WCD938X_HPH_CNP_WG_CTL (0x30CC)
#define WCD938X_HPH_CNP_WG_TIME (0x30CD)
#define WCD938X_HPH_OCP_CTL (0x30CE)
#define WCD938X_HPH_AUTO_CHOP (0x30CF)
#define WCD938X_HPH_CHOP_CTL (0x30D0)
#define WCD938X_HPH_PA_CTL1 (0x30D1)
#define WCD938X_HPH_PA_CTL2 (0x30D2)
#define WCD938X_HPHPA_GND_R_MASK BIT(6)
#define WCD938X_HPHPA_GND_L_MASK BIT(4)
#define WCD938X_HPH_L_EN (0x30D3)
#define WCD938X_HPH_L_TEST (0x30D4)
#define WCD938X_HPH_L_ATEST (0x30D5)
#define WCD938X_HPH_R_EN (0x30D6)
#define WCD938X_GAIN_SRC_SEL_MASK BIT(5)
#define WCD938X_GAIN_SRC_SEL_REGISTER 1
#define WCD938X_HPH_R_TEST (0x30D7)
#define WCD938X_HPH_R_ATEST (0x30D8)
#define WCD938X_HPHPA_GND_OVR_MASK BIT(1)
#define WCD938X_HPH_RDAC_CLK_CTL1 (0x30D9)
#define WCD938X_CHOP_CLK_EN_MASK BIT(7)
#define WCD938X_HPH_RDAC_CLK_CTL2 (0x30DA)
#define WCD938X_HPH_RDAC_LDO_CTL (0x30DB)
#define WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL (0x30DC)
#define WCD938X_HPH_REFBUFF_UHQA_CTL (0x30DD)
#define WCD938X_HPH_REFBUFF_LP_CTL (0x30DE)
#define WCD938X_PREREF_FLIT_BYPASS_MASK BIT(0)
#define WCD938X_HPH_L_DAC_CTL (0x30DF)
#define WCD938X_HPH_R_DAC_CTL (0x30E0)
#define WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL (0x30E1)
#define WCD938X_HPH_SURGE_HPHLR_SURGE_EN (0x30E2)
#define WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1 (0x30E3)
#define WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS (0x30E4)
#define WCD938X_EAR_EAR_EN_REG (0x30E9)
#define WCD938X_EAR_EAR_PA_CON (0x30EA)
#define WCD938X_EAR_EAR_SP_CON (0x30EB)
#define WCD938X_EAR_EAR_DAC_CON (0x30EC)
#define WCD938X_DAC_SAMPLE_EDGE_SEL_MASK BIT(7)
#define WCD938X_EAR_EAR_CNP_FSM_CON (0x30ED)
#define WCD938X_EAR_TEST_CTL (0x30EE)
#define WCD938X_EAR_STATUS_REG_1 (0x30EF)
#define WCD938X_EAR_STATUS_REG_2 (0x30F0)
#define WCD938X_ANA_NEW_PAGE_REGISTER (0x3100)
#define WCD938X_HPH_NEW_ANA_HPH2 (0x3101)
#define WCD938X_HPH_NEW_ANA_HPH3 (0x3102)
#define WCD938X_SLEEP_CTL (0x3103)
#define WCD938X_SLEEP_WATCHDOG_CTL (0x3104)
#define WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL (0x311F)
#define WCD938X_MBHC_NEW_CTL_1 (0x3120)
#define WCD938X_MBHC_CTL_RCO_EN_MASK BIT(7)
#define WCD938X_MBHC_CTL_RCO_EN BIT(7)
#define WCD938X_MBHC_BTN_DBNC_MASK GENMASK(1, 0)
#define WCD938X_MBHC_BTN_DBNC_T_16_MS 0x2
#define WCD938X_MBHC_NEW_CTL_2 (0x3121)
#define WCD938X_M_RTH_CTL_MASK GENMASK(3, 2)
#define WCD938X_MBHC_HS_VREF_CTL_MASK GENMASK(1, 0)
#define WCD938X_MBHC_HS_VREF_1P5_V 0x1
#define WCD938X_MBHC_NEW_PLUG_DETECT_CTL (0x3122)
#define WCD938X_MBHC_DBNC_TIMER_INSREM_DBNC_T_96_MS 0x6
#define WCD938X_MBHC_NEW_ZDET_ANA_CTL (0x3123)
#define WCD938X_ZDET_RANGE_CTL_MASK GENMASK(3, 0)
#define WCD938X_ZDET_MAXV_CTL_MASK GENMASK(6, 4)
#define WCD938X_MBHC_NEW_ZDET_RAMP_CTL (0x3124)
#define WCD938X_MBHC_NEW_FSM_STATUS (0x3125)
#define WCD938X_MBHC_NEW_ADC_RESULT (0x3126)
#define WCD938X_TX_NEW_AMIC_MUX_CFG (0x3127)
#define WCD938X_AUX_AUXPA (0x3128)
#define WCD938X_AUXPA_CLK_EN_MASK BIT(4)
#define WCD938X_LDORXTX_MODE (0x3129)
#define WCD938X_LDORXTX_CONFIG (0x312A)
#define WCD938X_DIE_CRACK_DIE_CRK_DET_EN (0x312C)
#define WCD938X_DIE_CRACK_DIE_CRK_DET_OUT (0x312D)
#define WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL (0x3132)
#define WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L (0x3133)
#define WCD938X_HPH_NEW_INT_RDAC_VREF_CTL (0x3134)
#define WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL (0x3135)
#define WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R (0x3136)
#define WCD938X_HPH_RES_DIV_MASK GENMASK(4, 0)
#define WCD938X_HPH_NEW_INT_PA_MISC1 (0x3137)
#define WCD938X_HPH_NEW_INT_PA_MISC2 (0x3138)
#define WCD938X_HPH_NEW_INT_PA_RDAC_MISC (0x3139)
#define WCD938X_HPH_NEW_INT_HPH_TIMER1 (0x313A)
#define WCD938X_AUTOCHOP_TIMER_EN BIT(1)
#define WCD938X_HPH_NEW_INT_HPH_TIMER2 (0x313B)
#define WCD938X_HPH_NEW_INT_HPH_TIMER3 (0x313C)
#define WCD938X_HPH_NEW_INT_HPH_TIMER4 (0x313D)
#define WCD938X_HPH_NEW_INT_PA_RDAC_MISC2 (0x313E)
#define WCD938X_HPH_NEW_INT_PA_RDAC_MISC3 (0x313F)
#define WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW (0x3140)
#define WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW (0x3141)
#define WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI (0x3145)
#define WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP (0x3146)
#define WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP (0x3147)
#define WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL (0x31AF)
#define WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL (0x31B0)
#define WCD938X_MOISTURE_EN_POLLING_MASK BIT(2)
#define WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT (0x31B1)
#define WCD938X_HSDET_PULLUP_C_MASK GENMASK(4, 0)
#define WCD938X_MBHC_NEW_INT_SPARE_2 (0x31B2)
#define WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON (0x31B7)
#define WCD938X_EAR_INT_NEW_CNP_VCM_CON1 (0x31B8)
#define WCD938X_EAR_INT_NEW_CNP_VCM_CON2 (0x31B9)
#define WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS (0x31BA)
#define WCD938X_AUX_INT_EN_REG (0x31BD)
#define WCD938X_AUX_INT_PA_CTRL (0x31BE)
#define WCD938X_AUX_INT_SP_CTRL (0x31BF)
#define WCD938X_AUX_INT_DAC_CTRL (0x31C0)
#define WCD938X_AUX_INT_CLK_CTRL (0x31C1)
#define WCD938X_AUX_INT_TEST_CTRL (0x31C2)
#define WCD938X_AUX_INT_STATUS_REG (0x31C3)
#define WCD938X_AUX_INT_MISC (0x31C4)
#define WCD938X_LDORXTX_INT_BIAS (0x31C5)
#define WCD938X_LDORXTX_INT_STB_LOADS_DTEST (0x31C6)
#define WCD938X_LDORXTX_INT_TEST0 (0x31C7)
#define WCD938X_LDORXTX_INT_STARTUP_TIMER (0x31C8)
#define WCD938X_LDORXTX_INT_TEST1 (0x31C9)
#define WCD938X_LDORXTX_INT_STATUS (0x31CA)
#define WCD938X_SLEEP_INT_WATCHDOG_CTL_1 (0x31D0)
#define WCD938X_SLEEP_INT_WATCHDOG_CTL_2 (0x31D1)
#define WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1 (0x31D3)
#define WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2 (0x31D4)
#define WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2 (0x31D5)
#define WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1 (0x31D6)
#define WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0 (0x31D7)
#define WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M (0x31D8)
#define WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M (0x31D9)
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1 (0x31DA)
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0 (0x31DB)
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP (0x31DC)
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1 (0x31DD)
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0 (0x31DE)
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP (0x31DF)
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0 (0x31E0)
#define WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP (0x31E1)
#define WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1 (0x31E2)
#define WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP (0x31E3)
#define WCD938X_TX_COM_NEW_INT_TXADC_INT_L2 (0x31E4)
#define WCD938X_TX_COM_NEW_INT_TXADC_INT_L1 (0x31E5)
#define WCD938X_TX_COM_NEW_INT_TXADC_INT_L0 (0x31E6)
#define WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP (0x31E7)
#define WCD938X_DIGITAL_PAGE_REGISTER (0x3400)
#define WCD938X_DIGITAL_CHIP_ID0 (0x3401)
#define WCD938X_DIGITAL_CHIP_ID1 (0x3402)
#define WCD938X_DIGITAL_CHIP_ID2 (0x3403)
#define WCD938X_DIGITAL_CHIP_ID3 (0x3404)
#define WCD938X_DIGITAL_SWR_TX_CLK_RATE (0x3405)
#define WCD938X_DIGITAL_CDC_RST_CTL (0x3406)
#define WCD938X_DIGITAL_TOP_CLK_CFG (0x3407)
#define WCD938X_DIGITAL_CDC_ANA_CLK_CTL (0x3408)
#define WCD938X_ANA_RX_CLK_EN_MASK BIT(0)
#define WCD938X_ANA_RX_DIV2_CLK_EN_MASK BIT(1)
#define WCD938X_ANA_RX_DIV4_CLK_EN_MASK BIT(2)
#define WCD938X_ANA_TX_CLK_EN_MASK BIT(3)
#define WCD938X_ANA_TX_DIV2_CLK_EN_MASK BIT(4)
#define WCD938X_ANA_TX_DIV4_CLK_EN_MASK BIT(5)
#define WCD938X_DIGITAL_CDC_DIG_CLK_CTL (0x3409)
#define WCD938X_TXD3_CLK_EN_MASK BIT(7)
#define WCD938X_TXD2_CLK_EN_MASK BIT(6)
#define WCD938X_TXD1_CLK_EN_MASK BIT(5)
#define WCD938X_TXD0_CLK_EN_MASK BIT(4)
#define WCD938X_TX_CLK_EN_MASK GENMASK(7, 4)
#define WCD938X_RXD2_CLK_EN_MASK BIT(2)
#define WCD938X_RXD1_CLK_EN_MASK BIT(1)
#define WCD938X_RXD0_CLK_EN_MASK BIT(0)
#define WCD938X_DIGITAL_SWR_RST_EN (0x340A)
#define WCD938X_DIGITAL_CDC_PATH_MODE (0x340B)
#define WCD938X_DIGITAL_CDC_RX_RST (0x340C)
#define WCD938X_DIGITAL_CDC_RX0_CTL (0x340D)
#define WCD938X_DEM_DITHER_ENABLE_MASK BIT(6)
#define WCD938X_DIGITAL_CDC_RX1_CTL (0x340E)
#define WCD938X_DIGITAL_CDC_RX2_CTL (0x340F)
#define WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1 (0x3410)
#define WCD938X_TXD0_MODE_MASK GENMASK(3, 0)
#define WCD938X_TXD1_MODE_MASK GENMASK(7, 4)
#define WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3 (0x3411)
#define WCD938X_TXD2_MODE_MASK GENMASK(3, 0)
#define WCD938X_TXD3_MODE_MASK GENMASK(7, 4)
#define WCD938X_DIGITAL_CDC_COMP_CTL_0 (0x3414)
#define WCD938X_HPHR_COMP_EN_MASK BIT(0)
#define WCD938X_HPHL_COMP_EN_MASK BIT(1)
#define WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL (0x3417)
#define WCD938X_TX_SC_CLK_EN_MASK BIT(0)
#define WCD938X_DIGITAL_CDC_HPH_DSM_A1_0 (0x3418)
#define WCD938X_DIGITAL_CDC_HPH_DSM_A1_1 (0x3419)
#define WCD938X_DIGITAL_CDC_HPH_DSM_A2_0 (0x341A)
#define WCD938X_DIGITAL_CDC_HPH_DSM_A2_1 (0x341B)
#define WCD938X_DIGITAL_CDC_HPH_DSM_A3_0 (0x341C)
#define WCD938X_DIGITAL_CDC_HPH_DSM_A3_1 (0x341D)
#define WCD938X_DIGITAL_CDC_HPH_DSM_A4_0 (0x341E)
#define WCD938X_DIGITAL_CDC_HPH_DSM_A4_1 (0x341F)
#define WCD938X_DIGITAL_CDC_HPH_DSM_A5_0 (0x3420)
#define WCD938X_DIGITAL_CDC_HPH_DSM_A5_1 (0x3421)
#define WCD938X_DIGITAL_CDC_HPH_DSM_A6_0 (0x3422)
#define WCD938X_DIGITAL_CDC_HPH_DSM_A7_0 (0x3423)
#define WCD938X_DIGITAL_CDC_HPH_DSM_C_0 (0x3424)
#define WCD938X_DIGITAL_CDC_HPH_DSM_C_1 (0x3425)
#define WCD938X_DIGITAL_CDC_HPH_DSM_C_2 (0x3426)
#define WCD938X_DIGITAL_CDC_HPH_DSM_C_3 (0x3427)
#define WCD938X_DIGITAL_CDC_HPH_DSM_R1 (0x3428)
#define WCD938X_DIGITAL_CDC_HPH_DSM_R2 (0x3429)
#define WCD938X_DIGITAL_CDC_HPH_DSM_R3 (0x342A)
#define WCD938X_DIGITAL_CDC_HPH_DSM_R4 (0x342B)
#define WCD938X_DIGITAL_CDC_HPH_DSM_R5 (0x342C)
#define WCD938X_DIGITAL_CDC_HPH_DSM_R6 (0x342D)
#define WCD938X_DIGITAL_CDC_HPH_DSM_R7 (0x342E)
#define WCD938X_DIGITAL_CDC_AUX_DSM_A1_0 (0x342F)
#define WCD938X_DIGITAL_CDC_AUX_DSM_A1_1 (0x3430)
#define WCD938X_DIGITAL_CDC_AUX_DSM_A2_0 (0x3431)
#define WCD938X_DIGITAL_CDC_AUX_DSM_A2_1 (0x3432)
#define WCD938X_DIGITAL_CDC_AUX_DSM_A3_0 (0x3433)
#define WCD938X_DIGITAL_CDC_AUX_DSM_A3_1 (0x3434)
#define WCD938X_DIGITAL_CDC_AUX_DSM_A4_0 (0x3435)
#define WCD938X_DIGITAL_CDC_AUX_DSM_A4_1 (0x3436)
#define WCD938X_DIGITAL_CDC_AUX_DSM_A5_0 (0x3437)
#define WCD938X_DIGITAL_CDC_AUX_DSM_A5_1 (0x3438)
#define WCD938X_DIGITAL_CDC_AUX_DSM_A6_0 (0x3439)
#define WCD938X_DIGITAL_CDC_AUX_DSM_A7_0 (0x343A)
#define WCD938X_DIGITAL_CDC_AUX_DSM_C_0 (0x343B)
#define WCD938X_DIGITAL_CDC_AUX_DSM_C_1 (0x343C)
#define WCD938X_DIGITAL_CDC_AUX_DSM_C_2 (0x343D)
#define WCD938X_DIGITAL_CDC_AUX_DSM_C_3 (0x343E)
#define WCD938X_DIGITAL_CDC_AUX_DSM_R1 (0x343F)
#define WCD938X_DIGITAL_CDC_AUX_DSM_R2 (0x3440)
#define WCD938X_DIGITAL_CDC_AUX_DSM_R3 (0x3441)
#define WCD938X_DIGITAL_CDC_AUX_DSM_R4 (0x3442)
#define WCD938X_DIGITAL_CDC_AUX_DSM_R5 (0x3443)
#define WCD938X_DIGITAL_CDC_AUX_DSM_R6 (0x3444)
#define WCD938X_DIGITAL_CDC_AUX_DSM_R7 (0x3445)
#define WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0 (0x3446)
#define WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1 (0x3447)
#define WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0 (0x3448)
#define WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1 (0x3449)
#define WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2 (0x344A)
#define WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0 (0x344B)
#define WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1 (0x344C)
#define WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2 (0x344D)
#define WCD938X_DIGITAL_CDC_HPH_GAIN_CTL (0x344E)
#define WCD938X_HPHL_RX_EN_MASK BIT(2)
#define WCD938X_HPHR_RX_EN_MASK BIT(3)
#define WCD938X_DIGITAL_CDC_AUX_GAIN_CTL (0x344F)
#define WCD938X_AUX_EN_MASK BIT(0)
#define WCD938X_DIGITAL_CDC_EAR_PATH_CTL (0x3450)
#define WCD938X_DIGITAL_CDC_SWR_CLH (0x3451)
#define WCD938X_DIGITAL_SWR_CLH_BYP (0x3452)
#define WCD938X_DIGITAL_CDC_TX0_CTL (0x3453)
#define WCD938X_DIGITAL_CDC_TX1_CTL (0x3454)
#define WCD938X_DIGITAL_CDC_TX2_CTL (0x3455)
#define WCD938X_DIGITAL_CDC_TX_RST (0x3456)
#define WCD938X_DIGITAL_CDC_REQ_CTL (0x3457)
#define WCD938X_FS_RATE_4P8_MASK BIT(1)
#define WCD938X_NO_NOTCH_MASK BIT(0)
#define WCD938X_DIGITAL_CDC_RST (0x3458)
#define WCD938X_DIGITAL_CDC_AMIC_CTL (0x345A)
#define WCD938X_AMIC1_IN_SEL_DMIC 0
#define WCD938X_AMIC1_IN_SEL_AMIC 0
#define WCD938X_AMIC1_IN_SEL_MASK BIT(0)
#define WCD938X_AMIC3_IN_SEL_MASK BIT(1)
#define WCD938X_AMIC4_IN_SEL_MASK BIT(2)
#define WCD938X_AMIC5_IN_SEL_MASK BIT(3)
#define WCD938X_DIGITAL_CDC_DMIC_CTL (0x345B)
#define WCD938X_DMIC_CLK_SCALING_EN_MASK GENMASK(2, 1)
#define WCD938X_DIGITAL_CDC_DMIC1_CTL (0x345C)
#define WCD938X_DMIC_CLK_EN_MASK BIT(3)
#define WCD938X_DIGITAL_CDC_DMIC2_CTL (0x345D)
#define WCD938X_DIGITAL_CDC_DMIC3_CTL (0x345E)
#define WCD938X_DIGITAL_CDC_DMIC4_CTL (0x345F)
#define WCD938X_DIGITAL_EFUSE_PRG_CTL (0x3460)
#define WCD938X_DIGITAL_EFUSE_CTL (0x3461)
#define WCD938X_DIGITAL_CDC_DMIC_RATE_1_2 (0x3462)
#define WCD938X_DIGITAL_CDC_DMIC_RATE_3_4 (0x3463)
#define WCD938X_DMIC1_RATE_MASK GENMASK(3, 0)
#define WCD938X_DMIC2_RATE_MASK GENMASK(7, 4)
#define WCD938X_DMIC3_RATE_MASK GENMASK(3, 0)
#define WCD938X_DMIC4_RATE_MASK GENMASK(7, 4)
#define WCD938X_DMIC4_RATE_2P4MHZ 3
#define WCD938X_DIGITAL_PDM_WD_CTL0 (0x3465)
#define WCD938X_PDM_WD_EN_MASK GENMASK(2, 0)
#define WCD938X_DIGITAL_PDM_WD_CTL1 (0x3466)
#define WCD938X_DIGITAL_PDM_WD_CTL2 (0x3467)
#define WCD938X_AUX_PDM_WD_EN_MASK GENMASK(2, 0)
#define WCD938X_DIGITAL_INTR_MODE (0x346A)
#define WCD938X_DIGITAL_INTR_MASK_0 (0x346B)
#define WCD938X_DIGITAL_INTR_MASK_1 (0x346C)
#define WCD938X_DIGITAL_INTR_MASK_2 (0x346D)
#define WCD938X_DIGITAL_INTR_STATUS_0 (0x346E)
#define WCD938X_DIGITAL_INTR_STATUS_1 (0x346F)
#define WCD938X_DIGITAL_INTR_STATUS_2 (0x3470)
#define WCD938X_DIGITAL_INTR_CLEAR_0 (0x3471)
#define WCD938X_DIGITAL_INTR_CLEAR_1 (0x3472)
#define WCD938X_DIGITAL_INTR_CLEAR_2 (0x3473)
#define WCD938X_DIGITAL_INTR_LEVEL_0 (0x3474)
#define WCD938X_DIGITAL_INTR_LEVEL_1 (0x3475)
#define WCD938X_DIGITAL_INTR_LEVEL_2 (0x3476)
#define WCD938X_DIGITAL_INTR_SET_0 (0x3477)
#define WCD938X_DIGITAL_INTR_SET_1 (0x3478)
#define WCD938X_DIGITAL_INTR_SET_2 (0x3479)
#define WCD938X_DIGITAL_INTR_TEST_0 (0x347A)
#define WCD938X_DIGITAL_INTR_TEST_1 (0x347B)
#define WCD938X_DIGITAL_INTR_TEST_2 (0x347C)
#define WCD938X_DIGITAL_TX_MODE_DBG_EN (0x347F)
#define WCD938X_DIGITAL_TX_MODE_DBG_0_1 (0x3480)
#define WCD938X_DIGITAL_TX_MODE_DBG_2_3 (0x3481)
#define WCD938X_DIGITAL_LB_IN_SEL_CTL (0x3482)
#define WCD938X_DIGITAL_LOOP_BACK_MODE (0x3483)
#define WCD938X_DIGITAL_SWR_DAC_TEST (0x3484)
#define WCD938X_DIGITAL_SWR_HM_TEST_RX_0 (0x3485)
#define WCD938X_DIGITAL_SWR_HM_TEST_TX_0 (0x3486)
#define WCD938X_DIGITAL_SWR_HM_TEST_RX_1 (0x3487)
#define WCD938X_DIGITAL_SWR_HM_TEST_TX_1 (0x3488)
#define WCD938X_DIGITAL_SWR_HM_TEST_TX_2 (0x3489)
#define WCD938X_DIGITAL_SWR_HM_TEST_0 (0x348A)
#define WCD938X_DIGITAL_SWR_HM_TEST_1 (0x348B)
#define WCD938X_DIGITAL_PAD_CTL_SWR_0 (0x348C)
#define WCD938X_DIGITAL_PAD_CTL_SWR_1 (0x348D)
#define WCD938X_DIGITAL_I2C_CTL (0x348E)
#define WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE (0x348F)
#define WCD938X_DIGITAL_EFUSE_TEST_CTL_0 (0x3490)
#define WCD938X_DIGITAL_EFUSE_TEST_CTL_1 (0x3491)
#define WCD938X_DIGITAL_EFUSE_T_DATA_0 (0x3492)
#define WCD938X_DIGITAL_EFUSE_T_DATA_1 (0x3493)
#define WCD938X_DIGITAL_PAD_CTL_PDM_RX0 (0x3494)
#define WCD938X_DIGITAL_PAD_CTL_PDM_RX1 (0x3495)
#define WCD938X_DIGITAL_PAD_CTL_PDM_TX0 (0x3496)
#define WCD938X_DIGITAL_PAD_CTL_PDM_TX1 (0x3497)
#define WCD938X_DIGITAL_PAD_CTL_PDM_TX2 (0x3498)
#define WCD938X_DIGITAL_PAD_INP_DIS_0 (0x3499)
#define WCD938X_DIGITAL_PAD_INP_DIS_1 (0x349A)
#define WCD938X_DIGITAL_DRIVE_STRENGTH_0 (0x349B)
#define WCD938X_DIGITAL_DRIVE_STRENGTH_1 (0x349C)
#define WCD938X_DIGITAL_DRIVE_STRENGTH_2 (0x349D)
#define WCD938X_DIGITAL_RX_DATA_EDGE_CTL (0x349E)
#define WCD938X_DIGITAL_TX_DATA_EDGE_CTL (0x349F)
#define WCD938X_DIGITAL_GPIO_MODE (0x34A0)
#define WCD938X_DIGITAL_PIN_CTL_OE (0x34A1)
#define WCD938X_DIGITAL_PIN_CTL_DATA_0 (0x34A2)
#define WCD938X_DIGITAL_PIN_CTL_DATA_1 (0x34A3)
#define WCD938X_DIGITAL_PIN_STATUS_0 (0x34A4)
#define WCD938X_DIGITAL_PIN_STATUS_1 (0x34A5)
#define WCD938X_DIGITAL_DIG_DEBUG_CTL (0x34A6)
#define WCD938X_DIGITAL_DIG_DEBUG_EN (0x34A7)
#define WCD938X_DIGITAL_ANA_CSR_DBG_ADD (0x34A8)
#define WCD938X_DIGITAL_ANA_CSR_DBG_CTL (0x34A9)
#define WCD938X_DIGITAL_SSP_DBG (0x34AA)
#define WCD938X_DIGITAL_MODE_STATUS_0 (0x34AB)
#define WCD938X_DIGITAL_MODE_STATUS_1 (0x34AC)
#define WCD938X_DIGITAL_SPARE_0 (0x34AD)
#define WCD938X_DIGITAL_SPARE_1 (0x34AE)
#define WCD938X_DIGITAL_SPARE_2 (0x34AF)
#define WCD938X_DIGITAL_EFUSE_REG_0 (0x34B0)
#define WCD938X_ID_MASK GENMASK(4, 1)
#define WCD938X_DIGITAL_EFUSE_REG_1 (0x34B1)
#define WCD938X_DIGITAL_EFUSE_REG_2 (0x34B2)
#define WCD938X_DIGITAL_EFUSE_REG_3 (0x34B3)
#define WCD938X_DIGITAL_EFUSE_REG_4 (0x34B4)
#define WCD938X_DIGITAL_EFUSE_REG_5 (0x34B5)
#define WCD938X_DIGITAL_EFUSE_REG_6 (0x34B6)
#define WCD938X_DIGITAL_EFUSE_REG_7 (0x34B7)
#define WCD938X_DIGITAL_EFUSE_REG_8 (0x34B8)
#define WCD938X_DIGITAL_EFUSE_REG_9 (0x34B9)
#define WCD938X_DIGITAL_EFUSE_REG_10 (0x34BA)
#define WCD938X_DIGITAL_EFUSE_REG_11 (0x34BB)
#define WCD938X_DIGITAL_EFUSE_REG_12 (0x34BC)
#define WCD938X_DIGITAL_EFUSE_REG_13 (0x34BD)
#define WCD938X_DIGITAL_EFUSE_REG_14 (0x34BE)
#define WCD938X_DIGITAL_EFUSE_REG_15 (0x34BF)
#define WCD938X_DIGITAL_EFUSE_REG_16 (0x34C0)
#define WCD938X_DIGITAL_EFUSE_REG_17 (0x34C1)
#define WCD938X_DIGITAL_EFUSE_REG_18 (0x34C2)
#define WCD938X_DIGITAL_EFUSE_REG_19 (0x34C3)
#define WCD938X_DIGITAL_EFUSE_REG_20 (0x34C4)
#define WCD938X_DIGITAL_EFUSE_REG_21 (0x34C5)
#define WCD938X_DIGITAL_EFUSE_REG_22 (0x34C6)
#define WCD938X_DIGITAL_EFUSE_REG_23 (0x34C7)
#define WCD938X_DIGITAL_EFUSE_REG_24 (0x34C8)
#define WCD938X_DIGITAL_EFUSE_REG_25 (0x34C9)
#define WCD938X_DIGITAL_EFUSE_REG_26 (0x34CA)
#define WCD938X_DIGITAL_EFUSE_REG_27 (0x34CB)
#define WCD938X_DIGITAL_EFUSE_REG_28 (0x34CC)
#define WCD938X_DIGITAL_EFUSE_REG_29 (0x34CD)
#define WCD938X_DIGITAL_EFUSE_REG_30 (0x34CE)
#define WCD938X_DIGITAL_EFUSE_REG_31 (0x34CF)
#define WCD938X_DIGITAL_TX_REQ_FB_CTL_0 (0x34D0)
#define WCD938X_DIGITAL_TX_REQ_FB_CTL_1 (0x34D1)
#define WCD938X_DIGITAL_TX_REQ_FB_CTL_2 (0x34D2)
#define WCD938X_DIGITAL_TX_REQ_FB_CTL_3 (0x34D3)
#define WCD938X_DIGITAL_TX_REQ_FB_CTL_4 (0x34D4)
#define WCD938X_DIGITAL_DEM_BYPASS_DATA0 (0x34D5)
#define WCD938X_DIGITAL_DEM_BYPASS_DATA1 (0x34D6)
#define WCD938X_DIGITAL_DEM_BYPASS_DATA2 (0x34D7)
#define WCD938X_DIGITAL_DEM_BYPASS_DATA3 (0x34D8)
#define WCD938X_MAX_REGISTER (WCD938X_DIGITAL_DEM_BYPASS_DATA3)
#define WCD938X_MAX_SWR_PORTS 5
#define WCD938X_MAX_TX_SWR_PORTS 4
#define WCD938X_MAX_SWR_CH_IDS 15
struct wcd938x_sdw_ch_info {
int port_num;
unsigned int ch_mask;
};
#define WCD_SDW_CH(id, pn, cmask) \
[id] = { \
.port_num = pn, \
.ch_mask = cmask, \
}
enum wcd938x_tx_sdw_ports {
WCD938X_ADC_1_2_PORT = 1,
WCD938X_ADC_3_4_PORT,
/* DMIC0_0, DMIC0_1, DMIC1_0, DMIC1_1 */
WCD938X_DMIC_0_3_MBHC_PORT,
WCD938X_DMIC_4_7_PORT,
};
enum wcd938x_tx_sdw_channels {
WCD938X_ADC1,
WCD938X_ADC2,
WCD938X_ADC3,
WCD938X_ADC4,
WCD938X_DMIC0,
WCD938X_DMIC1,
WCD938X_MBHC,
WCD938X_DMIC2,
WCD938X_DMIC3,
WCD938X_DMIC4,
WCD938X_DMIC5,
WCD938X_DMIC6,
WCD938X_DMIC7,
};
enum wcd938x_rx_sdw_ports {
WCD938X_HPH_PORT = 1,
WCD938X_CLSH_PORT,
WCD938X_COMP_PORT,
WCD938X_LO_PORT,
WCD938X_DSD_PORT,
};
enum wcd938x_rx_sdw_channels {
WCD938X_HPH_L,
WCD938X_HPH_R,
WCD938X_CLSH,
WCD938X_COMP_L,
WCD938X_COMP_R,
WCD938X_LO,
WCD938X_DSD_R,
WCD938X_DSD_L,
};
enum {
WCD938X_SDW_DIR_RX,
WCD938X_SDW_DIR_TX,
};
struct wcd938x_priv;
struct wcd938x_sdw_priv {
struct sdw_slave *sdev;
struct sdw_stream_config sconfig;
struct sdw_stream_runtime *sruntime;
struct sdw_port_config port_config[WCD938X_MAX_SWR_PORTS];
struct wcd938x_sdw_ch_info *ch_info;
bool port_enable[WCD938X_MAX_SWR_CH_IDS];
int port_map[WCD938X_MAX_SWR_PORTS];
int active_ports;
int num_ports;
bool is_tx;
struct wcd938x_priv *wcd938x;
};
extern struct regmap_config wcd938x_regmap_config;
int wcd938x_handle_sdw_irq(struct wcd938x_sdw_priv *priv);
#if IS_ENABLED(CONFIG_SND_SOC_WCD938X_SDW)
int wcd938x_sdw_free(struct wcd938x_sdw_priv *wcd,
struct snd_pcm_substream *substream,
struct snd_soc_dai *dai);
int wcd938x_sdw_set_sdw_stream(struct wcd938x_sdw_priv *wcd,
struct snd_soc_dai *dai,
void *stream, int direction);
int wcd938x_sdw_hw_params(struct wcd938x_sdw_priv *wcd,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai);
struct device *wcd938x_sdw_device_get(struct device_node *np);
int wcd938x_swr_get_current_bank(struct sdw_slave *sdev);
#else
static inline int wcd938x_sdw_free(struct wcd938x_sdw_priv *wcd,
struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
return -EOPNOTSUPP;
}
static inline int wcd938x_sdw_set_sdw_stream(struct wcd938x_sdw_priv *wcd,
struct snd_soc_dai *dai,
void *stream, int direction)
{
return -EOPNOTSUPP;
}
static inline int wcd938x_sdw_hw_params(struct wcd938x_sdw_priv *wcd,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
return -EOPNOTSUPP;
}
static inline struct device *wcd938x_sdw_device_get(struct device_node *np)
{
return NULL;
}
static inline int wcd938x_swr_get_current_bank(struct sdw_slave *sdev)
{
return 0;
}
#endif /* CONFIG_SND_SOC_WCD938X_SDW */
#endif /* __WCD938X_H__ */