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dt-bindings: PCI: Cleanup MediaTek binding text 

To accommodate other SoC generations, regroup specific properties by SoC,
and remove redundant descriptions.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
[bhelgaas: split into a rename patch and a cleanup patch]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Ryder Lee 2017-08-10 14:34:58 +08:00 committed by Bjorn Helgaas
parent d5a1092258
commit a9551ba609
1 changed files with 16 additions and 16 deletions
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32
Documentation/devicetree/bindings/pci/mediatek-pcie.txt
View File

@ -1,18 +1,13 @@
MediaTek Gen2 PCIe controller which is available on MT7623 series SoCs MediaTek Gen2 PCIe controller
PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root
ports supports a Gen2 1-lane Link and has PIPE interface to PHY.
Required properties: Required properties:
- compatible: Should contain "mediatek,mt7623-pcie". - compatible: Should contain one of the following strings:
"mediatek,mt2701-pcie"
"mediatek,mt7623-pcie"
- device_type: Must be "pci" - device_type: Must be "pci"
- reg: Base addresses and lengths of the PCIe controller. - reg: Base addresses and lengths of the PCIe controller.
- #address-cells: Address representation for root ports (must be 3) - #address-cells: Address representation for root ports (must be 3)
- #size-cells: Size representation for root ports (must be 2) - #size-cells: Size representation for root ports (must be 2)
- #interrupt-cells: Size representation for interrupts (must be 1)
- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
Please refer to the standard PCI bus binding document for a more detailed
explanation.
- clocks: Must contain an entry for each entry in clock-names. - clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details. See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries: - clock-names: Must include the following entries:
@ -20,12 +15,6 @@ Required properties:
- sys_ck0 :for clock of Port0 - sys_ck0 :for clock of Port0
- sys_ck1 :for clock of Port1 - sys_ck1 :for clock of Port1
- sys_ck2 :for clock of Port2 - sys_ck2 :for clock of Port2
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- pcie-rst0 :port0 reset
- pcie-rst1 :port1 reset
- pcie-rst2 :port2 reset
- phys: List of PHY specifiers (used by generic PHY framework). - phys: List of PHY specifiers (used by generic PHY framework).
- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
number of PHYs as specified in *phys* property. number of PHYs as specified in *phys* property.
@ -34,6 +23,16 @@ Required properties:
- bus-range: Range of bus numbers associated with this controller. - bus-range: Range of bus numbers associated with this controller.
- ranges: Ranges for the PCI memory and I/O regions. - ranges: Ranges for the PCI memory and I/O regions.
Required properties for MT7623/MT2701:
- #interrupt-cells: Size representation for interrupts (must be 1)
- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
Please refer to the standard PCI bus binding document for a more detailed
explanation.
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
number of root ports.
In addition, the device tree node must have sub-nodes describing each In addition, the device tree node must have sub-nodes describing each
PCIe port interface, having the following mandatory properties: PCIe port interface, having the following mandatory properties:
@ -85,7 +84,8 @@ Examples:
<&hifsys MT2701_HIFSYS_PCIE1_RST>, <&hifsys MT2701_HIFSYS_PCIE1_RST>,
<&hifsys MT2701_HIFSYS_PCIE2_RST>; <&hifsys MT2701_HIFSYS_PCIE2_RST>;
reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
phys = <&pcie0_phy>, <&pcie1_phy>, <&pcie2_phy>; phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
<&pcie2_phy PHY_TYPE_PCIE>;
phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
bus-range = <0x00 0xff>; bus-range = <0x00 0xff>;