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sfc: Work around unreliable legacy interrupt status
In rare cases, reading the legacy interrupt status register can acknowledge an event queue whose attention flag has not yet been set in the register. Until we service this event queue it will not generate any more interrupts. Therefore, as a secondary check, poll the next slot in each active event queue whose flag is not set. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1435,6 +1435,7 @@ static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
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{
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struct efx_nic *efx = dev_id;
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efx_oword_t *int_ker = efx->irq_status.addr;
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irqreturn_t result = IRQ_NONE;
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struct efx_channel *channel;
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efx_dword_t reg;
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u32 queues;
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@ -1449,23 +1450,24 @@ static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
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if (unlikely(syserr))
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return falcon_fatal_interrupt(efx);
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if (queues == 0)
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return IRQ_NONE;
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efx->last_irq_cpu = raw_smp_processor_id();
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EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
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irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
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/* Schedule processing of any interrupting queues */
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channel = &efx->channel[0];
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while (queues) {
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if (queues & 0x01)
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efx_for_each_channel(channel, efx) {
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if ((queues & 1) ||
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falcon_event_present(
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falcon_event(channel, channel->eventq_read_ptr))) {
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efx_schedule_channel(channel);
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channel++;
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result = IRQ_HANDLED;
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}
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queues >>= 1;
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}
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return IRQ_HANDLED;
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if (result == IRQ_HANDLED) {
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efx->last_irq_cpu = raw_smp_processor_id();
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EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
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irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
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}
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return result;
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}
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