mirror of https://gitee.com/openkylin/linux.git
dmaengine: omap-dma: more consolidation of CCR register setup
We can move the handling of the DMA synchronisation control out of the prepare functions; this can be pre-calculated when the DMA channel has been allocated, so we don't need to duplicate this in both prepare functions. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -41,6 +41,7 @@ struct omap_chan {
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struct list_head node;
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void __iomem *channel_base;
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const struct omap_dma_reg *reg_map;
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uint32_t ccr;
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struct dma_slave_config cfg;
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unsigned dma_sig;
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@ -552,6 +553,21 @@ static int omap_dma_alloc_chan_resources(struct dma_chan *chan)
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}
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}
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if (dma_omap1()) {
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if (__dma_omap16xx(od->plat->dma_attr)) {
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c->ccr = CCR_OMAP31_DISABLE;
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/* Duplicate what plat-omap/dma.c does */
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c->ccr |= c->dma_ch + 1;
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} else {
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c->ccr = c->dma_sig & 0x1f;
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}
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} else {
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c->ccr = c->dma_sig & 0x1f;
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c->ccr |= (c->dma_sig & ~0x1f) << 14;
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}
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if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
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c->ccr |= CCR_BUFFERING_DISABLE;
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return ret;
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}
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@ -787,7 +803,7 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
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d->dev_addr = dev_addr;
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d->es = es;
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d->ccr = CCR_SYNC_FRAME;
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d->ccr = c->ccr | CCR_SYNC_FRAME;
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if (dir == DMA_DEV_TO_MEM)
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d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT;
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else
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@ -797,14 +813,6 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
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d->csdp = es;
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if (dma_omap1()) {
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if (__dma_omap16xx(od->plat->dma_attr)) {
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d->ccr |= CCR_OMAP31_DISABLE;
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/* Duplicate what plat-omap/dma.c does */
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d->ccr |= c->dma_ch + 1;
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} else {
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d->ccr |= c->dma_sig & 0x1f;
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}
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d->cicr |= CICR_TOUT_IE;
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if (dir == DMA_DEV_TO_MEM)
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@ -812,16 +820,11 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
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else
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d->csdp |= CSDP_DST_PORT_TIPB | CSDP_SRC_PORT_EMIFF;
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} else {
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d->ccr |= (c->dma_sig & ~0x1f) << 14;
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d->ccr |= c->dma_sig & 0x1f;
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if (dir == DMA_DEV_TO_MEM)
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d->ccr |= CCR_TRIGGER_SRC;
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d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
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}
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if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
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d->ccr |= CCR_BUFFERING_DISABLE;
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if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS)
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d->clnk_ctrl = c->dma_ch;
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@ -903,7 +906,7 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
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d->sg[0].fn = buf_len / period_len;
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d->sglen = 1;
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d->ccr = 0;
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d->ccr = c->ccr;
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if (dir == DMA_DEV_TO_MEM)
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d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT;
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else
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@ -916,14 +919,6 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
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d->csdp = es;
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if (dma_omap1()) {
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if (__dma_omap16xx(od->plat->dma_attr)) {
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d->ccr |= CCR_OMAP31_DISABLE;
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/* Duplicate what plat-omap/dma.c does */
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d->ccr |= c->dma_ch + 1;
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} else {
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d->ccr |= c->dma_sig & 0x1f;
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}
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d->cicr |= CICR_TOUT_IE;
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if (dir == DMA_DEV_TO_MEM)
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@ -931,9 +926,6 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
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else
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d->csdp |= CSDP_DST_PORT_MPUI | CSDP_SRC_PORT_EMIFF;
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} else {
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d->ccr |= (c->dma_sig & ~0x1f) << 14;
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d->ccr |= c->dma_sig & 0x1f;
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if (burst)
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d->ccr |= CCR_SYNC_PACKET;
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else
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@ -946,8 +938,6 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
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d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64;
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}
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if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
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d->ccr |= CCR_BUFFERING_DISABLE;
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if (__dma_omap15xx(od->plat->dma_attr))
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d->ccr |= CCR_AUTO_INIT | CCR_REPEAT;
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