mirror of https://gitee.com/openkylin/linux.git
x86/resctrl: Move all the macros to resctrl/internal.h
Move all the macros to resctrl/internal.h and rename the registers with MSR_ prefix for consistency. [bp: align MSR definitions vertically ] Signed-off-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: "Chang S. Bae" <chang.seok.bae@intel.com> Cc: David Miller <davem@davemloft.net> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Dmitry Safonov <dima@arista.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jann Horn <jannh@google.com> Cc: Joerg Roedel <jroedel@suse.de> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Kate Stewart <kstewart@linuxfoundation.org> Cc: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> Cc: <linux-doc@vger.kernel.org> Cc: Mauro Carvalho Chehab <mchehab+samsung@kernel.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Philippe Ombredanne <pombredanne@nexb.com> Cc: Pu Wen <puwen@hygon.cn> Cc: <qianyue.zj@alibaba-inc.com> Cc: "Rafael J. Wysocki" <rafael@kernel.org> Cc: Reinette Chatre <reinette.chatre@intel.com> Cc: Rian Hunter <rian@alum.mit.edu> Cc: Sherry Hurwitz <sherry.hurwitz@amd.com> Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Thomas Lendacky <Thomas.Lendacky@amd.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Vitaly Kuznetsov <vkuznets@redhat.com> Cc: <xiaochen.shen@intel.com> Link: https://lkml.kernel.org/r/20181121202811.4492-5-babu.moger@amd.com
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@ -33,9 +33,6 @@
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#include <asm/resctrl_sched.h>
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#include "internal.h"
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#define MBA_IS_LINEAR 0x4
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#define MBA_MAX_MBPS U32_MAX
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/* Mutex to protect rdtgroup access. */
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DEFINE_MUTEX(rdtgroup_mutex);
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@ -72,7 +69,7 @@ struct rdt_resource rdt_resources_all[] = {
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.rid = RDT_RESOURCE_L3,
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.name = "L3",
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.domains = domain_init(RDT_RESOURCE_L3),
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.msr_base = IA32_L3_CBM_BASE,
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.msr_base = MSR_IA32_L3_CBM_BASE,
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.msr_update = cat_wrmsr,
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.cache_level = 3,
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.cache = {
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@ -89,7 +86,7 @@ struct rdt_resource rdt_resources_all[] = {
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.rid = RDT_RESOURCE_L3DATA,
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.name = "L3DATA",
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.domains = domain_init(RDT_RESOURCE_L3DATA),
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.msr_base = IA32_L3_CBM_BASE,
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.msr_base = MSR_IA32_L3_CBM_BASE,
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.msr_update = cat_wrmsr,
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.cache_level = 3,
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.cache = {
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@ -106,7 +103,7 @@ struct rdt_resource rdt_resources_all[] = {
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.rid = RDT_RESOURCE_L3CODE,
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.name = "L3CODE",
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.domains = domain_init(RDT_RESOURCE_L3CODE),
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.msr_base = IA32_L3_CBM_BASE,
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.msr_base = MSR_IA32_L3_CBM_BASE,
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.msr_update = cat_wrmsr,
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.cache_level = 3,
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.cache = {
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@ -123,7 +120,7 @@ struct rdt_resource rdt_resources_all[] = {
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.rid = RDT_RESOURCE_L2,
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.name = "L2",
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.domains = domain_init(RDT_RESOURCE_L2),
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.msr_base = IA32_L2_CBM_BASE,
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.msr_base = MSR_IA32_L2_CBM_BASE,
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.msr_update = cat_wrmsr,
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.cache_level = 2,
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.cache = {
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@ -140,7 +137,7 @@ struct rdt_resource rdt_resources_all[] = {
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.rid = RDT_RESOURCE_L2DATA,
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.name = "L2DATA",
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.domains = domain_init(RDT_RESOURCE_L2DATA),
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.msr_base = IA32_L2_CBM_BASE,
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.msr_base = MSR_IA32_L2_CBM_BASE,
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.msr_update = cat_wrmsr,
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.cache_level = 2,
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.cache = {
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@ -157,7 +154,7 @@ struct rdt_resource rdt_resources_all[] = {
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.rid = RDT_RESOURCE_L2CODE,
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.name = "L2CODE",
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.domains = domain_init(RDT_RESOURCE_L2CODE),
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.msr_base = IA32_L2_CBM_BASE,
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.msr_base = MSR_IA32_L2_CBM_BASE,
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.msr_update = cat_wrmsr,
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.cache_level = 2,
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.cache = {
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@ -174,7 +171,7 @@ struct rdt_resource rdt_resources_all[] = {
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.rid = RDT_RESOURCE_MBA,
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.name = "MB",
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.domains = domain_init(RDT_RESOURCE_MBA),
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.msr_base = IA32_MBA_THRTL_BASE,
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.msr_base = MSR_IA32_MBA_THRTL_BASE,
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.msr_update = mba_wrmsr,
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.cache_level = 3,
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.parse_ctrlval = parse_bw,
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@ -211,9 +208,10 @@ static inline void cache_alloc_hsw_probe(void)
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struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3];
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u32 l, h, max_cbm = BIT_MASK(20) - 1;
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if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
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if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0))
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return;
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rdmsr(IA32_L3_CBM_BASE, l, h);
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rdmsr(MSR_IA32_L3_CBM_BASE, l, h);
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/* If all the bits were set in MSR, return success */
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if (l != max_cbm)
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@ -6,15 +6,18 @@
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#include <linux/kernfs.h>
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#include <linux/jump_label.h>
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#define IA32_L3_QOS_CFG 0xc81
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#define IA32_L2_QOS_CFG 0xc82
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#define IA32_L3_CBM_BASE 0xc90
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#define IA32_L2_CBM_BASE 0xd10
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#define IA32_MBA_THRTL_BASE 0xd50
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#define MSR_IA32_L3_QOS_CFG 0xc81
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#define MSR_IA32_L2_QOS_CFG 0xc82
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#define MSR_IA32_L3_CBM_BASE 0xc90
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#define MSR_IA32_L2_CBM_BASE 0xd10
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#define MSR_IA32_MBA_THRTL_BASE 0xd50
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#define L3_QOS_CDP_ENABLE 0x01ULL
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#define MSR_IA32_QM_CTR 0x0c8e
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#define MSR_IA32_QM_EVTSEL 0x0c8d
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#define L2_QOS_CDP_ENABLE 0x01ULL
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#define L3_QOS_CDP_ENABLE 0x01ULL
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#define L2_QOS_CDP_ENABLE 0x01ULL
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/*
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* Event IDs are used to program IA32_QM_EVTSEL before reading event
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@ -29,6 +32,8 @@
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#define MBM_CNTR_WIDTH 24
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#define MBM_OVERFLOW_INTERVAL 1000
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#define MAX_MBA_BW 100u
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#define MBA_IS_LINEAR 0x4
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#define MBA_MAX_MBPS U32_MAX
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#define RMID_VAL_ERROR BIT_ULL(63)
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#define RMID_VAL_UNAVAIL BIT_ULL(62)
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@ -28,9 +28,6 @@
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#include <asm/cpu_device_id.h>
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#include "internal.h"
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#define MSR_IA32_QM_CTR 0x0c8e
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#define MSR_IA32_QM_EVTSEL 0x0c8d
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struct rmid_entry {
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u32 rmid;
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int busy;
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@ -1722,14 +1722,14 @@ static void l3_qos_cfg_update(void *arg)
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{
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bool *enable = arg;
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wrmsrl(IA32_L3_QOS_CFG, *enable ? L3_QOS_CDP_ENABLE : 0ULL);
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wrmsrl(MSR_IA32_L3_QOS_CFG, *enable ? L3_QOS_CDP_ENABLE : 0ULL);
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}
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static void l2_qos_cfg_update(void *arg)
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{
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bool *enable = arg;
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wrmsrl(IA32_L2_QOS_CFG, *enable ? L2_QOS_CDP_ENABLE : 0ULL);
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wrmsrl(MSR_IA32_L2_QOS_CFG, *enable ? L2_QOS_CDP_ENABLE : 0ULL);
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}
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static inline bool is_mba_linear(void)
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