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drm/nouveau/gr/gf100-: virtualise init_504430 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2018-05-08 20:39:46 +10:00
parent f3ef80c0c4
commit ab4d49a349
8 changed files with 21 additions and 3 deletions
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2
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
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@ -2092,6 +2092,8 @@ gf100_gr_init(struct gf100_gr *gr)
if (gr->func->init_tex_hww_esr) if (gr->func->init_tex_hww_esr)
gr->func->init_tex_hww_esr(gr, gpc, tpc); gr->func->init_tex_hww_esr(gr, gpc, tpc);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
if (gr->func->init_504430)
gr->func->init_504430(gr, gpc, tpc);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
} }

3
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
View File

@ -139,6 +139,7 @@ struct gf100_gr_func {
void (*init_419c9c)(struct gf100_gr *); void (*init_419c9c)(struct gf100_gr *);
void (*init_ppc_exceptions)(struct gf100_gr *); void (*init_ppc_exceptions)(struct gf100_gr *);
void (*init_tex_hww_esr)(struct gf100_gr *, int gpc, int tpc); void (*init_tex_hww_esr)(struct gf100_gr *, int gpc, int tpc);
void (*init_504430)(struct gf100_gr *, int gpc, int tpc);
void (*set_hww_esr_report_mask)(struct gf100_gr *); void (*set_hww_esr_report_mask)(struct gf100_gr *);
const struct gf100_gr_pack *mmio; const struct gf100_gr_pack *mmio;
struct { struct {
@ -175,6 +176,8 @@ void gk104_gr_init_sked_hww_esr(struct gf100_gr *);
void gk110_gr_init_419eb4(struct gf100_gr *); void gk110_gr_init_419eb4(struct gf100_gr *);
void gm107_gr_init_504430(struct gf100_gr *, int, int);
int gk20a_gr_init(struct gf100_gr *); int gk20a_gr_init(struct gf100_gr *);
int gm200_gr_rops(struct gf100_gr *); int gm200_gr_rops(struct gf100_gr *);

10
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
View File

@ -281,6 +281,13 @@ gm107_gr_pack_mmio[] = {
* PGRAPH engine/subdev functions * PGRAPH engine/subdev functions
******************************************************************************/ ******************************************************************************/
void
gm107_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000);
}
static void static void
gm107_gr_init_bios_2(struct gf100_gr *gr) gm107_gr_init_bios_2(struct gf100_gr *gr)
{ {
@ -395,7 +402,7 @@ gm107_gr_init(struct gf100_gr *gr)
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
gr->func->init_tex_hww_esr(gr, gpc, tpc); gr->func->init_tex_hww_esr(gr, gpc, tpc);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); gr->func->init_504430(gr, gpc, tpc);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005);
} }
@ -459,6 +466,7 @@ gm107_gr = {
.init_419cc0 = gf100_gr_init_419cc0, .init_419cc0 = gf100_gr_init_419cc0,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions, .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr, .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_504430 = gm107_gr_init_504430,
.mmio = gm107_gr_pack_mmio, .mmio = gm107_gr_pack_mmio,
.fecs.ucode = &gm107_gr_fecs_ucode, .fecs.ucode = &gm107_gr_fecs_ucode,
.gpccs.ucode = &gm107_gr_gpccs_ucode, .gpccs.ucode = &gm107_gr_gpccs_ucode,

3
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
View File

@ -123,7 +123,7 @@ gm200_gr_init(struct gf100_gr *gr)
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
gr->func->init_tex_hww_esr(gr, gpc, tpc); gr->func->init_tex_hww_esr(gr, gpc, tpc);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); gr->func->init_504430(gr, gpc, tpc);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005);
} }
@ -205,6 +205,7 @@ gm200_gr = {
.init_419cc0 = gf100_gr_init_419cc0, .init_419cc0 = gf100_gr_init_419cc0,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions, .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr, .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_504430 = gm107_gr_init_504430,
.rops = gm200_gr_rops, .rops = gm200_gr_rops,
.ppc_nr = 2, .ppc_nr = 2,
.grctx = &gm200_grctx, .grctx = &gm200_grctx,

3
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c
View File

@ -103,7 +103,7 @@ gp100_gr_init(struct gf100_gr *gr)
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
gr->func->init_tex_hww_esr(gr, gpc, tpc); gr->func->init_tex_hww_esr(gr, gpc, tpc);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); gr->func->init_504430(gr, gpc, gpc);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000105); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000105);
} }
@ -145,6 +145,7 @@ gp100_gr = {
.init_419c9c = gp100_gr_init_419c9c, .init_419c9c = gp100_gr_init_419c9c,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions, .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr, .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_504430 = gm107_gr_init_504430,
.rops = gm200_gr_rops, .rops = gm200_gr_rops,
.ppc_nr = 2, .ppc_nr = 2,
.grctx = &gp100_grctx, .grctx = &gp100_grctx,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c
View File

@ -55,6 +55,7 @@ gp102_gr = {
.init_419cc0 = gf100_gr_init_419cc0, .init_419cc0 = gf100_gr_init_419cc0,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions, .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr, .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_504430 = gm107_gr_init_504430,
.rops = gm200_gr_rops, .rops = gm200_gr_rops,
.ppc_nr = 3, .ppc_nr = 3,
.grctx = &gp102_grctx, .grctx = &gp102_grctx,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c
View File

@ -41,6 +41,7 @@ gp107_gr = {
.init_419cc0 = gf100_gr_init_419cc0, .init_419cc0 = gf100_gr_init_419cc0,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions, .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr, .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_504430 = gm107_gr_init_504430,
.rops = gm200_gr_rops, .rops = gm200_gr_rops,
.ppc_nr = 1, .ppc_nr = 1,
.grctx = &gp107_grctx, .grctx = &gp107_grctx,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c
View File

@ -39,6 +39,7 @@ gp10b_gr = {
.init_419cc0 = gf100_gr_init_419cc0, .init_419cc0 = gf100_gr_init_419cc0,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions, .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.init_tex_hww_esr = gf100_gr_init_tex_hww_esr, .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
.init_504430 = gm107_gr_init_504430,
.rops = gm200_gr_rops, .rops = gm200_gr_rops,
.ppc_nr = 1, .ppc_nr = 1,
.grctx = &gp102_grctx, .grctx = &gp102_grctx,