mirror of https://gitee.com/openkylin/linux.git
Blackfin: add support for the Acvilon BF561 board
Signed-off-by: Valentin Yakovenkov <yakovenkov@gmail.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Valentin Yakovenkov
Mike Frysinger
parent
b2e8dbd204
commit
ab843c7940
File diff suppressed because it is too large
Load Diff
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@ -19,4 +19,11 @@ config BFIN561_BLUETECHNIX_CM
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help
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CM-BF561 support for EVAL- and DEV-Board.
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config BFIN561_ACVILON
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bool "BF561-ACVILON"
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help
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BF561-ACVILON System On Module support (SO-DIMM 144).
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For more information about Acvilon BF561 SoM
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please go to http://www.niistt.ru/
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endchoice
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@ -2,6 +2,7 @@
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# arch/blackfin/mach-bf561/boards/Makefile
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#
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obj-$(CONFIG_BFIN561_ACVILON) += acvilon.o
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obj-$(CONFIG_BFIN561_BLUETECHNIX_CM) += cm_bf561.o
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obj-$(CONFIG_BFIN561_EZKIT) += ezkit.o
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obj-$(CONFIG_BFIN561_TEPLA) += tepla.o
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@ -0,0 +1,551 @@
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/*
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* File: arch/blackfin/mach-bf561/acvilon.c
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* Based on: arch/blackfin/mach-bf561/ezkit.c
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* Author:
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*
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* Created:
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* Description:
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*
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* Modified:
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* Copyright 2004-2006 Analog Devices Inc.
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* Copyright 2009 CJSC "NII STT"
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*
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* Bugs:
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*
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* For more information about Acvilon BF561 SoM please
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* go to http://www.niistt.ru/
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*
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*/
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/plat-ram.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/i2c-pca-platform.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <asm/dma.h>
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#include <asm/bfin5xx_spi.h>
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#include <asm/portmux.h>
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#include <asm/dpmc.h>
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#include <asm/cacheflush.h>
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#include <linux/i2c.h>
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/*
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* Name the Board for the /proc/cpuinfo
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*/
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const char bfin_board_name[] = "Acvilon board";
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#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
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#include <linux/usb/isp1760.h>
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static struct resource bfin_isp1760_resources[] = {
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[0] = {
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.start = 0x20000000,
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.end = 0x20000000 + 0x000fffff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_PF15,
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.end = IRQ_PF15,
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.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
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},
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};
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static struct isp1760_platform_data isp1760_priv = {
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.is_isp1761 = 0,
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.port1_disable = 0,
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.bus_width_16 = 1,
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.port1_otg = 0,
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.analog_oc = 0,
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.dack_polarity_high = 0,
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.dreq_polarity_high = 0,
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};
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static struct platform_device bfin_isp1760_device = {
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.name = "isp1760-hcd",
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.id = 0,
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.dev = {
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.platform_data = &isp1760_priv,
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},
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.num_resources = ARRAY_SIZE(bfin_isp1760_resources),
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.resource = bfin_isp1760_resources,
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};
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#endif
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static struct resource bfin_i2c_pca_resources[] = {
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{
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.name = "pca9564-regs",
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.start = 0x2C000000,
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.end = 0x2C000000 + 16,
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
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}, {
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.start = IRQ_PF8,
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.end = IRQ_PF8,
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.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
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},
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};
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struct i2c_pca9564_pf_platform_data pca9564_platform_data = {
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.gpio = -1,
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.i2c_clock_speed = 330000,
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.timeout = 10000
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};
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/* PCA9564 I2C Bus driver */
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static struct platform_device bfin_i2c_pca_device = {
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.name = "i2c-pca-platform",
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.id = 0,
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.num_resources = ARRAY_SIZE(bfin_i2c_pca_resources),
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.resource = bfin_i2c_pca_resources,
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.dev = {
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.platform_data = &pca9564_platform_data,
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}
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};
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/* I2C devices fitted. */
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static struct i2c_board_info acvilon_i2c_devs[] __initdata = {
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{
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I2C_BOARD_INFO("ds1339", 0x68),
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},
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{
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I2C_BOARD_INFO("tcn75", 0x49),
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},
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};
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#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
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static struct platdata_mtd_ram mtd_ram_data = {
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.mapname = "rootfs(RAM)",
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.bankwidth = 4,
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};
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static struct resource mtd_ram_resource = {
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.start = 0x4000000,
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.end = 0x5ffffff,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device mtd_ram_device = {
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.name = "mtd-ram",
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.id = 0,
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.dev = {
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.platform_data = &mtd_ram_data,
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},
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.num_resources = 1,
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.resource = &mtd_ram_resource,
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};
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#endif
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#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
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#include <linux/smsc911x.h>
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static struct resource smsc911x_resources[] = {
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{
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.name = "smsc911x-memory",
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.start = 0x28000000,
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.end = 0x28000000 + 0xFF,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = IRQ_PF7,
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.end = IRQ_PF7,
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.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
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},
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};
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static struct smsc911x_platform_config smsc911x_config = {
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.flags = SMSC911X_USE_32BIT,
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.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
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.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
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.phy_interface = PHY_INTERFACE_MODE_MII,
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};
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static struct platform_device smsc911x_device = {
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.name = "smsc911x",
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.id = 0,
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.num_resources = ARRAY_SIZE(smsc911x_resources),
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.resource = smsc911x_resources,
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.dev = {
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.platform_data = &smsc911x_config,
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},
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};
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#endif
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#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
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#ifdef CONFIG_SERIAL_BFIN_UART0
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static struct resource bfin_uart0_resources[] = {
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{
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.start = BFIN_UART_THR,
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.end = BFIN_UART_GCTL + 2,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = IRQ_UART_RX,
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.end = IRQ_UART_RX + 1,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = IRQ_UART_ERROR,
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.end = IRQ_UART_ERROR,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = CH_UART_TX,
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.end = CH_UART_TX,
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.flags = IORESOURCE_DMA,
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},
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{
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.start = CH_UART_RX,
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.end = CH_UART_RX,
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.flags = IORESOURCE_DMA,
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},
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};
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unsigned short bfin_uart0_peripherals[] = {
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P_UART0_TX, P_UART0_RX, 0
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};
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static struct platform_device bfin_uart0_device = {
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.name = "bfin-uart",
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.id = 0,
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.num_resources = ARRAY_SIZE(bfin_uart0_resources),
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.resource = bfin_uart0_resources,
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.dev = {
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/* Passed to driver */
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.platform_data = &bfin_uart0_peripherals,
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},
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};
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#endif
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#endif
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#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
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#ifdef CONFIG_MTD_PARTITIONS
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const char *part_probes[] = { "cmdlinepart", NULL };
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static struct mtd_partition bfin_plat_nand_partitions[] = {
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{
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.name = "params(nand)",
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.size = 32 * 1024 * 1024,
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.offset = 0,
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}, {
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.name = "userfs(nand)",
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.size = MTDPART_SIZ_FULL,
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.offset = MTDPART_OFS_APPEND,
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},
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};
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#endif
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#define BFIN_NAND_PLAT_CLE 2
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#define BFIN_NAND_PLAT_ALE 3
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static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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if (cmd == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_CLE)
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writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
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else
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writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
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}
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#define BFIN_NAND_PLAT_READY GPIO_PF10
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static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
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{
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return gpio_get_value(BFIN_NAND_PLAT_READY);
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}
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static struct platform_nand_data bfin_plat_nand_data = {
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.chip = {
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.chip_delay = 30,
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#ifdef CONFIG_MTD_PARTITIONS
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.part_probe_types = part_probes,
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.partitions = bfin_plat_nand_partitions,
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.nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
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#endif
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},
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.ctrl = {
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.cmd_ctrl = bfin_plat_nand_cmd_ctrl,
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.dev_ready = bfin_plat_nand_dev_ready,
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},
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};
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#define MAX(x, y) (x > y ? x : y)
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static struct resource bfin_plat_nand_resources = {
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.start = 0x24000000,
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.end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
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.flags = IORESOURCE_IO,
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};
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static struct platform_device bfin_async_nand_device = {
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.name = "gen_nand",
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.id = -1,
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.num_resources = 1,
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.resource = &bfin_plat_nand_resources,
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.dev = {
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.platform_data = &bfin_plat_nand_data,
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},
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};
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static void bfin_plat_nand_init(void)
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{
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gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
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}
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#else
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static void bfin_plat_nand_init(void)
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{
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}
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#endif
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#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
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static struct mtd_partition bfin_spi_dataflash_partitions[] = {
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{
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.name = "bootloader",
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.size = 0x4200,
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.offset = 0,
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.mask_flags = MTD_CAP_ROM},
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{
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.name = "u-boot",
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.size = 0x42000,
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.offset = MTDPART_OFS_APPEND,
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},
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{
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.name = "u-boot(params)",
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.size = 0x4200,
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.offset = MTDPART_OFS_APPEND,
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},
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{
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.name = "kernel",
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.size = 0x294000,
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.offset = MTDPART_OFS_APPEND,
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},
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{
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.name = "params",
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.size = 0x42000,
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.offset = MTDPART_OFS_APPEND,
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},
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{
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.name = "rootfs",
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.size = MTDPART_SIZ_FULL,
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.offset = MTDPART_OFS_APPEND,
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}
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};
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static struct flash_platform_data bfin_spi_dataflash_data = {
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.name = "SPI Dataflash",
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.parts = bfin_spi_dataflash_partitions,
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.nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
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};
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/* DataFlash chip */
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static struct bfin5xx_spi_chip data_flash_chip_info = {
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.enable_dma = 0, /* use dma transfer with this chip */
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.bits_per_word = 8,
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};
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#endif
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#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
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static struct bfin5xx_spi_chip spidev_chip_info = {
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.enable_dma = 0,
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.bits_per_word = 8,
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};
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#endif
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#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
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/* SPI (0) */
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static struct resource bfin_spi0_resource[] = {
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[0] = {
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.start = SPI0_REGBASE,
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.end = SPI0_REGBASE + 0xFF,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = CH_SPI,
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.end = CH_SPI,
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.flags = IORESOURCE_DMA,
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},
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[2] = {
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.start = IRQ_SPI,
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.end = IRQ_SPI,
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.flags = IORESOURCE_IRQ,
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},
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};
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/* SPI controller data */
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static struct bfin5xx_spi_master bfin_spi0_info = {
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.num_chipselect = 8,
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.enable_dma = 1, /* master has the ability to do dma transfer */
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.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
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};
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static struct platform_device bfin_spi0_device = {
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.name = "bfin-spi",
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.id = 0, /* Bus number */
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.num_resources = ARRAY_SIZE(bfin_spi0_resource),
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.resource = bfin_spi0_resource,
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.dev = {
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.platform_data = &bfin_spi0_info, /* Passed to driver */
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},
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};
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#endif
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static struct spi_board_info bfin_spi_board_info[] __initdata = {
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#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
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{
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.modalias = "spidev",
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.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
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.bus_num = 0,
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.chip_select = 3,
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.controller_data = &spidev_chip_info,
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},
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#endif
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#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
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{ /* DataFlash chip */
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.modalias = "mtd_dataflash",
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.max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
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.bus_num = 0, /* Framework bus number */
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.chip_select = 2, /* Framework chip select */
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.platform_data = &bfin_spi_dataflash_data,
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.controller_data = &data_flash_chip_info,
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.mode = SPI_MODE_3,
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},
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#endif
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};
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static struct resource bfin_gpios_resources = {
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.start = 31,
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/* .end = MAX_BLACKFIN_GPIOS - 1, */
|
||||
.end = 32,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
};
|
||||
|
||||
static struct platform_device bfin_gpios_device = {
|
||||
.name = "simple-gpio",
|
||||
.id = -1,
|
||||
.num_resources = 1,
|
||||
.resource = &bfin_gpios_resources,
|
||||
};
|
||||
|
||||
static const unsigned int cclk_vlev_datasheet[] = {
|
||||
VRPAIR(VLEV_085, 250000000),
|
||||
VRPAIR(VLEV_090, 300000000),
|
||||
VRPAIR(VLEV_095, 313000000),
|
||||
VRPAIR(VLEV_100, 350000000),
|
||||
VRPAIR(VLEV_105, 400000000),
|
||||
VRPAIR(VLEV_110, 444000000),
|
||||
VRPAIR(VLEV_115, 450000000),
|
||||
VRPAIR(VLEV_120, 475000000),
|
||||
VRPAIR(VLEV_125, 500000000),
|
||||
VRPAIR(VLEV_130, 600000000),
|
||||
};
|
||||
|
||||
static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
|
||||
.tuple_tab = cclk_vlev_datasheet,
|
||||
.tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
|
||||
.vr_settling_time = 25 /* us */ ,
|
||||
};
|
||||
|
||||
static struct platform_device bfin_dpmc = {
|
||||
.name = "bfin dpmc",
|
||||
.dev = {
|
||||
.platform_data = &bfin_dmpc_vreg_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *acvilon_devices[] __initdata = {
|
||||
&bfin_dpmc,
|
||||
|
||||
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
|
||||
&bfin_spi0_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
&bfin_uart0_device,
|
||||
#endif
|
||||
#endif
|
||||
|
||||
&bfin_gpios_device,
|
||||
|
||||
#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
|
||||
&smsc911x_device,
|
||||
#endif
|
||||
|
||||
&bfin_i2c_pca_device,
|
||||
|
||||
#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
|
||||
&bfin_async_nand_device,
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
|
||||
&mtd_ram_device,
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
static int __init acvilon_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
printk(KERN_INFO "%s(): registering device resources\n", __func__);
|
||||
|
||||
bfin_plat_nand_init();
|
||||
ret =
|
||||
platform_add_devices(acvilon_devices, ARRAY_SIZE(acvilon_devices));
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
i2c_register_board_info(0, acvilon_i2c_devs,
|
||||
ARRAY_SIZE(acvilon_i2c_devs));
|
||||
|
||||
bfin_write_FIO0_FLAG_C(1 << 14);
|
||||
msleep(5);
|
||||
bfin_write_FIO0_FLAG_S(1 << 14);
|
||||
|
||||
spi_register_board_info(bfin_spi_board_info,
|
||||
ARRAY_SIZE(bfin_spi_board_info));
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(acvilon_init);
|
||||
|
||||
static struct platform_device *acvilon_early_devices[] __initdata = {
|
||||
#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
&bfin_uart0_device,
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
void __init native_machine_early_platform_add_devices(void)
|
||||
{
|
||||
printk(KERN_INFO "register early platform devices\n");
|
||||
early_platform_add_devices(acvilon_early_devices,
|
||||
ARRAY_SIZE(acvilon_early_devices));
|
||||
}
|
||||
Loading…
Reference in New Issue