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pinctrl: Add Pistachio SoC pin control binding document
Add a device-tree binding document for the pin controller present on the IMG Pistachio SoC. Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Andrew Bresticker
Linus Walleij
parent
a9ed9eb634
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Imagination Technologies Pistachio SoC pin controllers
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======================================================
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The pin controllers on Pistachio are a combined GPIO controller, (GPIO)
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interrupt controller, and pinmux + pinconf device. The system ("east") pin
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controller on Pistachio has 99 pins, 90 of which are MFIOs which can be
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configured as GPIOs. The 90 GPIOs are divided into 6 banks of up to 16 GPIOs
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each. The GPIO banks are represented as sub-nodes of the pad controller node.
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Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
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../interrupt-controller/interrupts.txt for generic information regarding
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pin controller, GPIO, and interrupt bindings.
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Required properties for pin controller node:
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--------------------------------------------
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- compatible: "img,pistachio-system-pinctrl".
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- reg: Address range of the pinctrl registers.
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Required properties for GPIO bank sub-nodes:
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--------------------------------------------
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- interrupts: Interrupt line for the GPIO bank.
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- gpio-controller: Indicates the device is a GPIO controller.
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- #gpio-cells: Must be two. The first cell is the GPIO pin number and the
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second cell indicates the polarity. See <dt-bindings/gpio/gpio.h> for
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a list of possible values.
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- interrupt-controller: Indicates the device is an interrupt controller.
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- #interrupt-cells: Must be two. The first cell is the GPIO pin number and
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the second cell encodes the interrupt flags. See
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<dt-bindings/interrupt-controller/irq.h> for a list of valid flags.
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Note that the N GPIO bank sub-nodes *must* be named gpio0, gpio1, ... gpioN-1.
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Required properties for pin configuration sub-nodes:
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----------------------------------------------------
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- pins: List of pins to which the configuration applies. See below for a
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list of possible pins.
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Optional properties for pin configuration sub-nodes:
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----------------------------------------------------
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- function: Mux function for the specified pins. This is not applicable for
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non-MFIO pins. See below for a list of valid functions for each pin.
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- bias-high-impedance: Enable high-impedance mode.
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- bias-pull-up: Enable weak pull-up.
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- bias-pull-down: Enable weak pull-down.
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- bias-bus-hold: Enable bus-keeper mode.
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- drive-strength: Drive strength in mA. Supported values: 2, 4, 8, 12.
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- input-schmitt-enable: Enable Schmitt trigger.
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- input-schmitt-disable: Disable Schmitt trigger.
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- slew-rate: Slew rate control. 0 for slow, 1 for fast.
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Pin Functions
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--- ---------
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mfio0 spim1
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mfio1 spim1, spim0, uart1
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mfio2 spim1, spim0, uart1
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mfio3 spim1
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mfio4 spim1
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mfio5 spim1
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mfio6 spim1
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mfio7 spim1
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mfio8 spim0
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mfio9 spim0
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mfio10 spim0
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mfio11 spis
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mfio12 spis
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mfio13 spis
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mfio14 spis
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mfio15 sdhost, mips_trace_clk, mips_trace_data
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mfio16 sdhost, mips_trace_dint, mips_trace_data
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mfio17 sdhost, mips_trace_trigout, mips_trace_data
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mfio18 sdhost, mips_trace_trigin, mips_trace_data
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mfio19 sdhost, mips_trace_dm, mips_trace_data
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mfio20 sdhost, mips_trace_probe_n, mips_trace_data
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mfio21 sdhost, mips_trace_data
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mfio22 sdhost, mips_trace_data
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mfio23 sdhost
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mfio24 sdhost
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mfio25 sdhost
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mfio26 sdhost
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mfio27 sdhost
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mfio28 i2c0, spim0
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mfio29 i2c0, spim0
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mfio30 i2c1, spim0
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mfio31 i2c1, spim1
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mfio32 i2c2
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mfio33 i2c2
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mfio34 i2c3
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mfio35 i2c3
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mfio36 i2s_out, audio_clk_in
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mfio37 i2s_out, debug_raw_cca_ind
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mfio38 i2s_out, debug_ed_sec20_cca_ind
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mfio39 i2s_out, debug_ed_sec40_cca_ind
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mfio40 i2s_out, debug_agc_done_0
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mfio41 i2s_out, debug_agc_done_1
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mfio42 i2s_out, debug_ed_cca_ind
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mfio43 i2s_out, debug_s2l_done
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mfio44 i2s_out
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mfio45 i2s_dac_clk, audio_sync
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mfio46 audio_trigger
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mfio47 i2s_in
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mfio48 i2s_in
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mfio49 i2s_in
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mfio50 i2s_in
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mfio51 i2s_in
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mfio52 i2s_in
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mfio53 i2s_in
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mfio54 i2s_in, spdif_in
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mfio55 uart0, spim0, spim1
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mfio56 uart0, spim0, spim1
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mfio57 uart0, spim0, spim1
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mfio58 uart0, spim1
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mfio59 uart1
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mfio60 uart1
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mfio61 spdif_out
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mfio62 spdif_in
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mfio63 eth, mips_trace_clk, mips_trace_data
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mfio64 eth, mips_trace_dint, mips_trace_data
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mfio65 eth, mips_trace_trigout, mips_trace_data
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mfio66 eth, mips_trace_trigin, mips_trace_data
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mfio67 eth, mips_trace_dm, mips_trace_data
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mfio68 eth, mips_trace_probe_n, mips_trace_data
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mfio69 eth, mips_trace_data
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mfio70 eth, mips_trace_data
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mfio71 eth
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mfio72 ir
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mfio73 pwmpdm, mips_trace_clk, sram_debug
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mfio74 pwmpdm, mips_trace_dint, sram_debug
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mfio75 pwmpdm, mips_trace_trigout, rom_debug
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mfio76 pwmpdm, mips_trace_trigin, rom_debug
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mfio77 mdc_debug, mips_trace_dm, rpu_debug
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mfio78 mdc_debug, mips_trace_probe_n, rpu_debug
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mfio79 ddr_debug, mips_trace_data, mips_debug
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mfio80 ddr_debug, mips_trace_data, mips_debug
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mfio81 dreq0, mips_trace_data, eth_debug
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mfio82 dreq1, mips_trace_data, eth_debug
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mfio83 mips_pll_lock, mips_trace_data, usb_debug
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mfio84 sys_pll_lock, mips_trace_data, usb_debug
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mfio85 wifi_pll_lock, mips_trace_data, sdhost_debug
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mfio86 bt_pll_lock, mips_trace_data, sdhost_debug
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mfio87 rpu_v_pll_lock, dreq2, socif_debug
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mfio88 rpu_l_pll_lock, dreq3, socif_debug
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mfio89 audio_pll_lock, dreq4, dreq5
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tck
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trstn
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tdi
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tms
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tdo
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jtag_comply
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safe_mode
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por_disable
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resetn
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Example:
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--------
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pinctrl@18101C00 {
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compatible = "img,pistachio-system-pinctrl";
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reg = <0x18101C00 0x400>;
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gpio0: gpio0 {
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interrupts = <GIC_SHARED 71 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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...
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gpio5: gpio5 {
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interrupts = <GIC_SHARED 76 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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...
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uart0_xfer: uart0-xfer {
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uart0-rxd {
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pins = "mfio55";
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function = "uart0";
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};
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uart0-txd {
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pins = "mfio56";
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function = "uart0";
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};
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};
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uart0_rts_cts: uart0-rts-cts {
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uart0-rts {
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pins = "mfio57";
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function = "uart0";
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};
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uart0-cts {
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pins = "mfio58";
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function = "uart0";
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};
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};
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};
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uart@... {
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...
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer>, <&uart0_rts_cts>;
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...
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};
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usb_vbus: fixed-regulator {
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...
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gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>;
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...
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};
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