mirror of https://gitee.com/openkylin/linux.git
pinctrl: sunxi: Add GR8 controller support
Just like the other member of the sunxi family, let's add a pinctrl table for the muxing options. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Mylène Josserand
Linus Walleij
parent
56e57cb6c0
commit
ac91ab51e4
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@ -23,6 +23,7 @@ Required properties:
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"allwinner,sun8i-h3-pinctrl"
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"allwinner,sun8i-h3-r-pinctrl"
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"allwinner,sun50i-a64-pinctrl"
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"nextthing,gr8-pinctrl"
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- reg: Should contain the register physical address and length for the
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pin controller.
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@ -17,6 +17,10 @@ config PINCTRL_SUN5I_A13
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def_bool MACH_SUN5I
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select PINCTRL_SUNXI
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config PINCTRL_GR8
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def_bool MACH_SUN5I
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select PINCTRL_SUNXI_COMMON
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config PINCTRL_SUN6I_A31
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def_bool MACH_SUN6I
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select PINCTRL_SUNXI
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@ -5,6 +5,7 @@ obj-y += pinctrl-sunxi.o
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obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
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obj-$(CONFIG_PINCTRL_SUN5I_A10S) += pinctrl-sun5i-a10s.o
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obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o
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obj-$(CONFIG_PINCTRL_GR8) += pinctrl-gr8.o
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obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
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obj-$(CONFIG_PINCTRL_SUN6I_A31S) += pinctrl-sun6i-a31s.o
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obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
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@ -0,0 +1,541 @@
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/*
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* NextThing GR8 SoCs pinctrl driver.
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*
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* Copyright (C) 2016 Mylene Josserand
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*
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* Based on pinctrl-sun5i-a13.c
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*
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* Mylene Josserand <mylene.josserand@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-sunxi.h"
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static const struct sunxi_desc_pin sun5i_gr8_pins[] = {
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "pwm0"),
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SUNXI_FUNCTION(0x3, "spdif"), /* DO */
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SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "ir0"), /* TX */
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SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "ir0"), /* RX */
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SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
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SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
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SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
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SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s0"), /* DO */
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SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s0"), /* DI */
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SUNXI_FUNCTION(0x3, "spdif"), /* DI */
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SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
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SUNXI_FUNCTION(0x3, "spdif"), /* DO */
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SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
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SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
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SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
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SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
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SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
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SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
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SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
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SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
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SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
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SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
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SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
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SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
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SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
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SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
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SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
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SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
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SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
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SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
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SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
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SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
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SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
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SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
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SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
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SUNXI_FUNCTION(0x3, "uart2"), /* RX */
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SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
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SUNXI_FUNCTION(0x3, "uart2")), /* TX */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
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SUNXI_FUNCTION(0x3, "uart2")), /* RX */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
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SUNXI_FUNCTION(0x3, "uart2")), /* CTS */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
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SUNXI_FUNCTION(0x3, "uart2")), /* RTS */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
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SUNXI_FUNCTION(0x3, "emac")), /* ECRS */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
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SUNXI_FUNCTION(0x3, "emac")), /* ECOL */
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
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SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
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SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
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SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
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SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
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SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
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SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
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SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
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SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
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SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
|
||||
SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
|
||||
SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
|
||||
SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
|
||||
SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
|
||||
SUNXI_FUNCTION(0x3, "emac")), /* ETXERR*/
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
|
||||
SUNXI_FUNCTION(0x3, "emac")), /* EMDC */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
|
||||
SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */
|
||||
/* Hole */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
|
||||
SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */
|
||||
SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
|
||||
SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
|
||||
SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */
|
||||
SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
|
||||
SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
|
||||
SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
|
||||
SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
|
||||
SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
|
||||
SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
|
||||
SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
|
||||
SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
|
||||
SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
|
||||
SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
|
||||
SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
|
||||
SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
|
||||
SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
|
||||
SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
|
||||
SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
|
||||
SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
|
||||
SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
|
||||
SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
|
||||
SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
|
||||
SUNXI_FUNCTION(0x4, "uart1")), /* TX */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
|
||||
SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
|
||||
SUNXI_FUNCTION(0x4, "uart1")), /* RX */
|
||||
/* Hole */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
|
||||
SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
|
||||
SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
|
||||
SUNXI_FUNCTION(0x4, "uart0")), /* TX */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
|
||||
SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
|
||||
SUNXI_FUNCTION(0x4, "uart0")), /* RX */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
|
||||
SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
|
||||
/* Hole */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x2, "gps"), /* CLK */
|
||||
SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x2, "gps"), /* SIGN */
|
||||
SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x2, "gps"), /* MAG */
|
||||
SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
|
||||
SUNXI_FUNCTION(0x3, "ms"), /* BS */
|
||||
SUNXI_FUNCTION(0x4, "uart1"), /* TX */
|
||||
SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
|
||||
SUNXI_FUNCTION(0x3, "ms"), /* CLK */
|
||||
SUNXI_FUNCTION(0x4, "uart1"), /* RX */
|
||||
SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
|
||||
SUNXI_FUNCTION(0x3, "ms"), /* D0 */
|
||||
SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
|
||||
SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
|
||||
SUNXI_FUNCTION(0x3, "ms"), /* D1 */
|
||||
SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
|
||||
SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
|
||||
SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
|
||||
SUNXI_FUNCTION(0x3, "ms"), /* D2 */
|
||||
SUNXI_FUNCTION(0x5, "uart2"), /* TX */
|
||||
SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
|
||||
SUNXI_FUNCTION(0x3, "ms"), /* D3 */
|
||||
SUNXI_FUNCTION(0x5, "uart2"), /* RX */
|
||||
SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
|
||||
SUNXI_FUNCTION(0x3, "uart3"), /* TX */
|
||||
SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
|
||||
SUNXI_FUNCTION(0x3, "uart3"), /* RX */
|
||||
SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
|
||||
SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
|
||||
SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
|
||||
SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
|
||||
SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
|
||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
|
||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
|
||||
SUNXI_FUNCTION(0x3, "pwm1"),
|
||||
SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
|
||||
SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
|
||||
};
|
||||
|
||||
static const struct sunxi_pinctrl_desc sun5i_gr8_pinctrl_data = {
|
||||
.pins = sun5i_gr8_pins,
|
||||
.npins = ARRAY_SIZE(sun5i_gr8_pins),
|
||||
.irq_banks = 1,
|
||||
};
|
||||
|
||||
static int sun5i_gr8_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return sunxi_pinctrl_init(pdev,
|
||||
&sun5i_gr8_pinctrl_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id sun5i_gr8_pinctrl_match[] = {
|
||||
{ .compatible = "nextthing,gr8-pinctrl", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sun5i_gr8_pinctrl_match);
|
||||
|
||||
static struct platform_driver sun5i_gr8_pinctrl_driver = {
|
||||
.probe = sun5i_gr8_pinctrl_probe,
|
||||
.driver = {
|
||||
.name = "gr8-pinctrl",
|
||||
.of_match_table = sun5i_gr8_pinctrl_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(sun5i_gr8_pinctrl_driver);
|
||||
|
||||
MODULE_AUTHOR("Mylene Josserand <mylene.josserand@free-electrons.com");
|
||||
MODULE_DESCRIPTION("NextThing GR8 pinctrl driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue