mirror of https://gitee.com/openkylin/linux.git
drm: omapdrm: Move num_ovls and num_mgrs to dispc_features structure
The num_ovls and num_mgrs are dispc features. Move them from the omap_dss_features structure to the dispc_features structure. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
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fcd4188894
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acf591c6aa
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@ -90,6 +90,8 @@ struct dispc_features {
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u8 num_fifos;
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u8 num_fifos;
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const enum omap_overlay_caps *overlay_caps;
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const enum omap_overlay_caps *overlay_caps;
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const u32 **supported_color_modes;
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const u32 **supported_color_modes;
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unsigned int num_mgrs;
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unsigned int num_ovls;
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unsigned int buffer_size_unit;
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unsigned int buffer_size_unit;
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unsigned int burst_size_unit;
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unsigned int burst_size_unit;
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@ -349,6 +351,16 @@ static void mgr_fld_write(enum omap_channel channel,
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spin_unlock_irqrestore(&dispc.control_lock, flags);
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spin_unlock_irqrestore(&dispc.control_lock, flags);
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}
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}
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static int dispc_get_num_ovls(void)
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{
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return dispc.feat->num_ovls;
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}
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static int dispc_get_num_mgrs(void)
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{
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return dispc.feat->num_mgrs;
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}
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#define SR(reg) \
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#define SR(reg) \
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dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
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dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
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#define RR(reg) \
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#define RR(reg) \
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@ -376,7 +388,7 @@ static void dispc_save_context(void)
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SR(CONFIG3);
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SR(CONFIG3);
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}
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}
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for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
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for (i = 0; i < dispc_get_num_mgrs(); i++) {
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SR(DEFAULT_COLOR(i));
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SR(DEFAULT_COLOR(i));
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SR(TRANS_COLOR(i));
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SR(TRANS_COLOR(i));
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SR(SIZE_MGR(i));
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SR(SIZE_MGR(i));
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@ -398,7 +410,7 @@ static void dispc_save_context(void)
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}
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}
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}
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}
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for (i = 0; i < dss_feat_get_num_ovls(); i++) {
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for (i = 0; i < dispc_get_num_ovls(); i++) {
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SR(OVL_BA0(i));
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SR(OVL_BA0(i));
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SR(OVL_BA1(i));
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SR(OVL_BA1(i));
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SR(OVL_POSITION(i));
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SR(OVL_POSITION(i));
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@ -482,7 +494,7 @@ static void dispc_restore_context(void)
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if (dss_has_feature(FEAT_MGR_LCD3))
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if (dss_has_feature(FEAT_MGR_LCD3))
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RR(CONFIG3);
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RR(CONFIG3);
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for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
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for (i = 0; i < dispc_get_num_mgrs(); i++) {
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RR(DEFAULT_COLOR(i));
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RR(DEFAULT_COLOR(i));
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RR(TRANS_COLOR(i));
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RR(TRANS_COLOR(i));
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RR(SIZE_MGR(i));
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RR(SIZE_MGR(i));
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@ -504,7 +516,7 @@ static void dispc_restore_context(void)
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}
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}
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}
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}
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for (i = 0; i < dss_feat_get_num_ovls(); i++) {
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for (i = 0; i < dispc_get_num_ovls(); i++) {
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RR(OVL_BA0(i));
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RR(OVL_BA0(i));
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RR(OVL_BA1(i));
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RR(OVL_BA1(i));
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RR(OVL_POSITION(i));
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RR(OVL_POSITION(i));
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@ -785,7 +797,7 @@ static void dispc_ovl_write_color_conv_coef(enum omap_plane_id plane,
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static void dispc_setup_color_conv_coef(void)
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static void dispc_setup_color_conv_coef(void)
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{
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{
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int i;
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int i;
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int num_ovl = dss_feat_get_num_ovls();
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int num_ovl = dispc_get_num_ovls();
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const struct color_conv_coef ctbl_bt601_5_ovl = {
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const struct color_conv_coef ctbl_bt601_5_ovl = {
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/* YUV -> RGB */
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/* YUV -> RGB */
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298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
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298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
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@ -877,7 +889,7 @@ static void dispc_ovl_enable_zorder_planes(void)
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if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
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if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
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return;
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return;
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for (i = 0; i < dss_feat_get_num_ovls(); i++)
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for (i = 0; i < dispc_get_num_ovls(); i++)
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REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
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REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
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}
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}
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@ -1134,7 +1146,7 @@ static void dispc_configure_burst_sizes(void)
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const int burst_size = BURST_SIZE_X8;
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const int burst_size = BURST_SIZE_X8;
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/* Configure burst size always to maximum size */
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/* Configure burst size always to maximum size */
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for (i = 0; i < dss_feat_get_num_ovls(); ++i)
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for (i = 0; i < dispc_get_num_ovls(); ++i)
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dispc_ovl_set_burst_size(i, burst_size);
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dispc_ovl_set_burst_size(i, burst_size);
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if (dispc.feat->has_writeback)
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if (dispc.feat->has_writeback)
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dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
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dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
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@ -1166,11 +1178,6 @@ static const u32 *dispc_ovl_get_color_modes(enum omap_plane_id plane)
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return dispc.feat->supported_color_modes[plane];
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return dispc.feat->supported_color_modes[plane];
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}
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}
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static int dispc_get_num_ovls(void)
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{
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return dss_feat_get_num_ovls();
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}
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static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
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static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
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{
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{
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if (channel == OMAP_DSS_CHANNEL_DIGIT)
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if (channel == OMAP_DSS_CHANNEL_DIGIT)
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@ -1285,7 +1292,7 @@ static void dispc_init_fifos(void)
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/*
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/*
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* Setup default fifo thresholds.
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* Setup default fifo thresholds.
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*/
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*/
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for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
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for (i = 0; i < dispc_get_num_ovls(); ++i) {
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u32 low, high;
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u32 low, high;
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const bool use_fifomerge = false;
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const bool use_fifomerge = false;
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const bool manual_update = false;
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const bool manual_update = false;
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@ -1389,7 +1396,7 @@ void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane,
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if (use_fifomerge) {
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if (use_fifomerge) {
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total_fifo_size = 0;
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total_fifo_size = 0;
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for (i = 0; i < dss_feat_get_num_ovls(); ++i)
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for (i = 0; i < dispc_get_num_ovls(); ++i)
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total_fifo_size += dispc_ovl_get_fifo_size(i);
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total_fifo_size += dispc_ovl_get_fifo_size(i);
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} else {
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} else {
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total_fifo_size = ovl_fifo_size;
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total_fifo_size = ovl_fifo_size;
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@ -1455,7 +1462,7 @@ static void dispc_init_mflag(void)
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(1 << 0) | /* MFLAG_CTRL = force always on */
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(1 << 0) | /* MFLAG_CTRL = force always on */
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(0 << 2)); /* MFLAG_START = disable */
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(0 << 2)); /* MFLAG_START = disable */
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for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
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for (i = 0; i < dispc_get_num_ovls(); ++i) {
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u32 size = dispc_ovl_get_fifo_size(i);
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u32 size = dispc_ovl_get_fifo_size(i);
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u32 unit = dispc.feat->buffer_size_unit;
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u32 unit = dispc.feat->buffer_size_unit;
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u32 low, high;
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u32 low, high;
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@ -2694,11 +2701,6 @@ void dispc_pck_free_enable(bool enable)
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REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
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REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
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}
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}
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static int dispc_get_num_mgrs(void)
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{
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return dss_feat_get_num_mgrs();
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}
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static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
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static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
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{
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{
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mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
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mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
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@ -3265,7 +3267,7 @@ static void dispc_dump_regs(struct seq_file *s)
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p_names = mgr_names;
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p_names = mgr_names;
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/* DISPC channel specific registers */
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/* DISPC channel specific registers */
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for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
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for (i = 0; i < dispc_get_num_mgrs(); i++) {
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DUMPREG(i, DISPC_DEFAULT_COLOR);
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DUMPREG(i, DISPC_DEFAULT_COLOR);
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DUMPREG(i, DISPC_TRANS_COLOR);
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DUMPREG(i, DISPC_TRANS_COLOR);
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DUMPREG(i, DISPC_SIZE_MGR);
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DUMPREG(i, DISPC_SIZE_MGR);
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@ -3291,7 +3293,7 @@ static void dispc_dump_regs(struct seq_file *s)
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p_names = ovl_names;
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p_names = ovl_names;
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for (i = 0; i < dss_feat_get_num_ovls(); i++) {
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for (i = 0; i < dispc_get_num_ovls(); i++) {
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DUMPREG(i, DISPC_OVL_BA0);
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DUMPREG(i, DISPC_OVL_BA0);
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DUMPREG(i, DISPC_OVL_BA1);
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DUMPREG(i, DISPC_OVL_BA1);
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DUMPREG(i, DISPC_OVL_POSITION);
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DUMPREG(i, DISPC_OVL_POSITION);
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@ -3369,7 +3371,7 @@ static void dispc_dump_regs(struct seq_file *s)
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/* Video pipeline coefficient registers */
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/* Video pipeline coefficient registers */
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/* start from OMAP_DSS_VIDEO1 */
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/* start from OMAP_DSS_VIDEO1 */
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for (i = 1; i < dss_feat_get_num_ovls(); i++) {
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for (i = 1; i < dispc_get_num_ovls(); i++) {
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for (j = 0; j < 8; j++)
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for (j = 0; j < 8; j++)
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DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
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DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
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@ -3890,6 +3892,8 @@ static const struct dispc_features omap24xx_dispc_feats = {
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.num_fifos = 3,
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.num_fifos = 3,
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.overlay_caps = omap2_dispc_overlay_caps,
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.overlay_caps = omap2_dispc_overlay_caps,
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.supported_color_modes = omap2_dispc_supported_color_modes,
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.supported_color_modes = omap2_dispc_supported_color_modes,
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.num_mgrs = 2,
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.num_ovls = 3,
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.buffer_size_unit = 1,
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.buffer_size_unit = 1,
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.burst_size_unit = 8,
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.burst_size_unit = 8,
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.no_framedone_tv = true,
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.no_framedone_tv = true,
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@ -3915,6 +3919,8 @@ static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
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.num_fifos = 3,
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.num_fifos = 3,
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.overlay_caps = omap3430_dispc_overlay_caps,
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.overlay_caps = omap3430_dispc_overlay_caps,
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.supported_color_modes = omap3_dispc_supported_color_modes,
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.supported_color_modes = omap3_dispc_supported_color_modes,
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.num_mgrs = 2,
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.num_ovls = 3,
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.buffer_size_unit = 1,
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.buffer_size_unit = 1,
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.burst_size_unit = 8,
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.burst_size_unit = 8,
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.no_framedone_tv = true,
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.no_framedone_tv = true,
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@ -3940,6 +3946,8 @@ static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
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.num_fifos = 3,
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.num_fifos = 3,
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.overlay_caps = omap3430_dispc_overlay_caps,
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.overlay_caps = omap3430_dispc_overlay_caps,
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.supported_color_modes = omap3_dispc_supported_color_modes,
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.supported_color_modes = omap3_dispc_supported_color_modes,
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.num_mgrs = 2,
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.num_ovls = 3,
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.buffer_size_unit = 1,
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.buffer_size_unit = 1,
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.burst_size_unit = 8,
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.burst_size_unit = 8,
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.no_framedone_tv = true,
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.no_framedone_tv = true,
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.num_fifos = 3,
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.num_fifos = 3,
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.overlay_caps = omap3630_dispc_overlay_caps,
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.overlay_caps = omap3630_dispc_overlay_caps,
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.supported_color_modes = omap3_dispc_supported_color_modes,
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.supported_color_modes = omap3_dispc_supported_color_modes,
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.num_mgrs = 2,
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.num_ovls = 3,
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.buffer_size_unit = 1,
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.burst_size_unit = 8,
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.no_framedone_tv = true,
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.set_max_preload = false,
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.last_pixel_inc_missing = true,
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};
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static const struct dispc_features am43xx_dispc_feats = {
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.sw_start = 7,
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.fp_start = 19,
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.bp_start = 31,
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.sw_max = 256,
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.vp_max = 4095,
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.hp_max = 4096,
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.mgr_width_start = 10,
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.mgr_height_start = 26,
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.mgr_width_max = 2048,
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.mgr_height_max = 2048,
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.max_lcd_pclk = 173000000,
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.max_tv_pclk = 59000000,
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.calc_scaling = dispc_ovl_calc_scaling_34xx,
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.calc_core_clk = calc_core_clk_34xx,
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.num_fifos = 3,
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.overlay_caps = omap3430_dispc_overlay_caps,
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.supported_color_modes = omap3_dispc_supported_color_modes,
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.num_mgrs = 1,
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.num_ovls = 3,
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.buffer_size_unit = 1,
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.buffer_size_unit = 1,
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.burst_size_unit = 8,
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.burst_size_unit = 8,
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.no_framedone_tv = true,
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.no_framedone_tv = true,
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.num_fifos = 5,
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.num_fifos = 5,
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.overlay_caps = omap4_dispc_overlay_caps,
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.overlay_caps = omap4_dispc_overlay_caps,
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.supported_color_modes = omap4_dispc_supported_color_modes,
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.supported_color_modes = omap4_dispc_supported_color_modes,
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.num_mgrs = 3,
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.num_ovls = 4,
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.buffer_size_unit = 16,
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.buffer_size_unit = 16,
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.burst_size_unit = 16,
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.burst_size_unit = 16,
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.gfx_fifo_workaround = true,
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.gfx_fifo_workaround = true,
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.num_fifos = 5,
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.num_fifos = 5,
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.overlay_caps = omap4_dispc_overlay_caps,
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.overlay_caps = omap4_dispc_overlay_caps,
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.supported_color_modes = omap4_dispc_supported_color_modes,
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.supported_color_modes = omap4_dispc_supported_color_modes,
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.num_mgrs = 4,
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.num_ovls = 4,
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.buffer_size_unit = 16,
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.buffer_size_unit = 16,
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.burst_size_unit = 16,
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.burst_size_unit = 16,
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.gfx_fifo_workaround = true,
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.gfx_fifo_workaround = true,
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@ -4278,7 +4319,7 @@ static const struct soc_device_attribute dispc_soc_devices[] = {
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.revision = "ES[12].?", .data = &omap34xx_rev1_0_dispc_feats },
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.revision = "ES[12].?", .data = &omap34xx_rev1_0_dispc_feats },
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{ .machine = "OMAP3[45]*", .data = &omap34xx_rev3_0_dispc_feats },
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{ .machine = "OMAP3[45]*", .data = &omap34xx_rev3_0_dispc_feats },
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{ .machine = "AM35*", .data = &omap34xx_rev3_0_dispc_feats },
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{ .machine = "AM35*", .data = &omap34xx_rev3_0_dispc_feats },
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{ .machine = "AM43*", .data = &omap34xx_rev3_0_dispc_feats },
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{ .machine = "AM43*", .data = &am43xx_dispc_feats },
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{ /* sentinel */ }
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{ /* sentinel */ }
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -4296,7 +4337,7 @@ static int dispc_bind(struct device *dev, struct device *master, void *data)
|
||||||
spin_lock_init(&dispc.control_lock);
|
spin_lock_init(&dispc.control_lock);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The OMAP34xx and OMAP36xx can't be told apart using the compatible
|
* The OMAP3-based models can't be told apart using the compatible
|
||||||
* string, use SoC device matching.
|
* string, use SoC device matching.
|
||||||
*/
|
*/
|
||||||
soc = soc_device_match(dispc_soc_devices);
|
soc = soc_device_match(dispc_soc_devices);
|
||||||
|
|
|
@ -44,8 +44,6 @@ struct omap_dss_features {
|
||||||
const enum dss_feat_id *features;
|
const enum dss_feat_id *features;
|
||||||
const int num_features;
|
const int num_features;
|
||||||
|
|
||||||
const int num_mgrs;
|
|
||||||
const int num_ovls;
|
|
||||||
const enum omap_dss_output_id *supported_outputs;
|
const enum omap_dss_output_id *supported_outputs;
|
||||||
const struct dss_param_range *dss_params;
|
const struct dss_param_range *dss_params;
|
||||||
};
|
};
|
||||||
|
@ -376,8 +374,6 @@ static const struct omap_dss_features omap2_dss_features = {
|
||||||
.features = omap2_dss_feat_list,
|
.features = omap2_dss_feat_list,
|
||||||
.num_features = ARRAY_SIZE(omap2_dss_feat_list),
|
.num_features = ARRAY_SIZE(omap2_dss_feat_list),
|
||||||
|
|
||||||
.num_mgrs = 2,
|
|
||||||
.num_ovls = 3,
|
|
||||||
.supported_outputs = omap2_dss_supported_outputs,
|
.supported_outputs = omap2_dss_supported_outputs,
|
||||||
.dss_params = omap2_dss_param_range,
|
.dss_params = omap2_dss_param_range,
|
||||||
};
|
};
|
||||||
|
@ -390,8 +386,6 @@ static const struct omap_dss_features omap3430_dss_features = {
|
||||||
.features = omap3430_dss_feat_list,
|
.features = omap3430_dss_feat_list,
|
||||||
.num_features = ARRAY_SIZE(omap3430_dss_feat_list),
|
.num_features = ARRAY_SIZE(omap3430_dss_feat_list),
|
||||||
|
|
||||||
.num_mgrs = 2,
|
|
||||||
.num_ovls = 3,
|
|
||||||
.supported_outputs = omap3430_dss_supported_outputs,
|
.supported_outputs = omap3430_dss_supported_outputs,
|
||||||
.dss_params = omap3_dss_param_range,
|
.dss_params = omap3_dss_param_range,
|
||||||
};
|
};
|
||||||
|
@ -407,8 +401,6 @@ static const struct omap_dss_features am35xx_dss_features = {
|
||||||
.features = am35xx_dss_feat_list,
|
.features = am35xx_dss_feat_list,
|
||||||
.num_features = ARRAY_SIZE(am35xx_dss_feat_list),
|
.num_features = ARRAY_SIZE(am35xx_dss_feat_list),
|
||||||
|
|
||||||
.num_mgrs = 2,
|
|
||||||
.num_ovls = 3,
|
|
||||||
.supported_outputs = omap3430_dss_supported_outputs,
|
.supported_outputs = omap3430_dss_supported_outputs,
|
||||||
.dss_params = omap3_dss_param_range,
|
.dss_params = omap3_dss_param_range,
|
||||||
};
|
};
|
||||||
|
@ -420,8 +412,6 @@ static const struct omap_dss_features am43xx_dss_features = {
|
||||||
.features = am43xx_dss_feat_list,
|
.features = am43xx_dss_feat_list,
|
||||||
.num_features = ARRAY_SIZE(am43xx_dss_feat_list),
|
.num_features = ARRAY_SIZE(am43xx_dss_feat_list),
|
||||||
|
|
||||||
.num_mgrs = 1,
|
|
||||||
.num_ovls = 3,
|
|
||||||
.supported_outputs = am43xx_dss_supported_outputs,
|
.supported_outputs = am43xx_dss_supported_outputs,
|
||||||
.dss_params = am43xx_dss_param_range,
|
.dss_params = am43xx_dss_param_range,
|
||||||
};
|
};
|
||||||
|
@ -433,8 +423,6 @@ static const struct omap_dss_features omap3630_dss_features = {
|
||||||
.features = omap3630_dss_feat_list,
|
.features = omap3630_dss_feat_list,
|
||||||
.num_features = ARRAY_SIZE(omap3630_dss_feat_list),
|
.num_features = ARRAY_SIZE(omap3630_dss_feat_list),
|
||||||
|
|
||||||
.num_mgrs = 2,
|
|
||||||
.num_ovls = 3,
|
|
||||||
.supported_outputs = omap3630_dss_supported_outputs,
|
.supported_outputs = omap3630_dss_supported_outputs,
|
||||||
.dss_params = omap3_dss_param_range,
|
.dss_params = omap3_dss_param_range,
|
||||||
};
|
};
|
||||||
|
@ -448,8 +436,6 @@ static const struct omap_dss_features omap4430_es1_0_dss_features = {
|
||||||
.features = omap4430_es1_0_dss_feat_list,
|
.features = omap4430_es1_0_dss_feat_list,
|
||||||
.num_features = ARRAY_SIZE(omap4430_es1_0_dss_feat_list),
|
.num_features = ARRAY_SIZE(omap4430_es1_0_dss_feat_list),
|
||||||
|
|
||||||
.num_mgrs = 3,
|
|
||||||
.num_ovls = 4,
|
|
||||||
.supported_outputs = omap4_dss_supported_outputs,
|
.supported_outputs = omap4_dss_supported_outputs,
|
||||||
.dss_params = omap4_dss_param_range,
|
.dss_params = omap4_dss_param_range,
|
||||||
};
|
};
|
||||||
|
@ -462,8 +448,6 @@ static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = {
|
||||||
.features = omap4430_es2_0_1_2_dss_feat_list,
|
.features = omap4430_es2_0_1_2_dss_feat_list,
|
||||||
.num_features = ARRAY_SIZE(omap4430_es2_0_1_2_dss_feat_list),
|
.num_features = ARRAY_SIZE(omap4430_es2_0_1_2_dss_feat_list),
|
||||||
|
|
||||||
.num_mgrs = 3,
|
|
||||||
.num_ovls = 4,
|
|
||||||
.supported_outputs = omap4_dss_supported_outputs,
|
.supported_outputs = omap4_dss_supported_outputs,
|
||||||
.dss_params = omap4_dss_param_range,
|
.dss_params = omap4_dss_param_range,
|
||||||
};
|
};
|
||||||
|
@ -476,8 +460,6 @@ static const struct omap_dss_features omap4_dss_features = {
|
||||||
.features = omap4_dss_feat_list,
|
.features = omap4_dss_feat_list,
|
||||||
.num_features = ARRAY_SIZE(omap4_dss_feat_list),
|
.num_features = ARRAY_SIZE(omap4_dss_feat_list),
|
||||||
|
|
||||||
.num_mgrs = 3,
|
|
||||||
.num_ovls = 4,
|
|
||||||
.supported_outputs = omap4_dss_supported_outputs,
|
.supported_outputs = omap4_dss_supported_outputs,
|
||||||
.dss_params = omap4_dss_param_range,
|
.dss_params = omap4_dss_param_range,
|
||||||
};
|
};
|
||||||
|
@ -490,23 +472,11 @@ static const struct omap_dss_features omap5_dss_features = {
|
||||||
.features = omap5_dss_feat_list,
|
.features = omap5_dss_feat_list,
|
||||||
.num_features = ARRAY_SIZE(omap5_dss_feat_list),
|
.num_features = ARRAY_SIZE(omap5_dss_feat_list),
|
||||||
|
|
||||||
.num_mgrs = 4,
|
|
||||||
.num_ovls = 4,
|
|
||||||
.supported_outputs = omap5_dss_supported_outputs,
|
.supported_outputs = omap5_dss_supported_outputs,
|
||||||
.dss_params = omap5_dss_param_range,
|
.dss_params = omap5_dss_param_range,
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Functions returning values related to a DSS feature */
|
/* Functions returning values related to a DSS feature */
|
||||||
int dss_feat_get_num_mgrs(void)
|
|
||||||
{
|
|
||||||
return omap_current_dss_features->num_mgrs;
|
|
||||||
}
|
|
||||||
|
|
||||||
int dss_feat_get_num_ovls(void)
|
|
||||||
{
|
|
||||||
return omap_current_dss_features->num_ovls;
|
|
||||||
}
|
|
||||||
|
|
||||||
unsigned long dss_feat_get_param_min(enum dss_range_param param)
|
unsigned long dss_feat_get_param_min(enum dss_range_param param)
|
||||||
{
|
{
|
||||||
return omap_current_dss_features->dss_params[param].min;
|
return omap_current_dss_features->dss_params[param].min;
|
||||||
|
|
|
@ -95,7 +95,4 @@ void dss_features_init(enum omapdss_version version);
|
||||||
|
|
||||||
enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel);
|
enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel);
|
||||||
|
|
||||||
int dss_feat_get_num_mgrs(void);
|
|
||||||
int dss_feat_get_num_ovls(void);
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
Loading…
Reference in New Issue