mirror of https://gitee.com/openkylin/linux.git
drm/amdgpu: Default disable GDS for compute VMIDs
The GDS and GWS blocks default to allowing all VMIDs to access all entries. Graphics VMIDs can handle setting these limits when the driver launches work. However, compute workloads under HWS control don't go through the kernel driver. Instead, HWS firmware should set these limits when a process is put into a VMID slot. Disable access to these devices by default by turning off all mask bits (for OA) and setting BASE=SIZE=0 (for GDS and GWS) for all compute VMIDs. If a process wants to use these resources, they can request this from the HWS firmware (when such capabilities are enabled). HWS will then handle setting the base and limit for the process when it is assigned to a VMID. This will also prevent user kernels from getting 'stuck' in GWS by accident if they write GWS-using code but HWS firmware is not set up to handle GWS reset. Until HWS is enabled to handle GWS properly, all GWS accesses will MEM_VIOL fault the kernel. v2: Move initialization outside of SRBM mutex Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1441,6 +1441,15 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
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}
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nv_grbm_select(adev, 0, 0, 0, 0);
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mutex_unlock(&adev->srbm_mutex);
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/* Initialize all compute VMIDs to have no GDS, GWS, or OA
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acccess. These should be enabled by FW for target VMIDs. */
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for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
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WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
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WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
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WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
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WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
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}
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}
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static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
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@ -1879,6 +1879,15 @@ static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
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}
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cik_srbm_select(adev, 0, 0, 0, 0);
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mutex_unlock(&adev->srbm_mutex);
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/* Initialize all compute VMIDs to have no GDS, GWS, or OA
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acccess. These should be enabled by FW for target VMIDs. */
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for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
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WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
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WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
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WREG32(amdgpu_gds_reg_offset[i].gws, 0);
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WREG32(amdgpu_gds_reg_offset[i].oa, 0);
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}
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}
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static void gfx_v7_0_config_init(struct amdgpu_device *adev)
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@ -3706,6 +3706,15 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
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}
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vi_srbm_select(adev, 0, 0, 0, 0);
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mutex_unlock(&adev->srbm_mutex);
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/* Initialize all compute VMIDs to have no GDS, GWS, or OA
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acccess. These should be enabled by FW for target VMIDs. */
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for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
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WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
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WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
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WREG32(amdgpu_gds_reg_offset[i].gws, 0);
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WREG32(amdgpu_gds_reg_offset[i].oa, 0);
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}
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}
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static void gfx_v8_0_config_init(struct amdgpu_device *adev)
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@ -1918,6 +1918,15 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
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}
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soc15_grbm_select(adev, 0, 0, 0, 0);
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mutex_unlock(&adev->srbm_mutex);
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/* Initialize all compute VMIDs to have no GDS, GWS, or OA
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acccess. These should be enabled by FW for target VMIDs. */
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for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
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WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
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WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
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WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
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WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
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}
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}
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static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
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