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x86: coding style fixes to arch/x86/kernel/cpu/cyrix.c 

Before:
   total: 46 errors, 10 warnings, 450 lines checked
After:
   total: 1 errors, 10 warnings, 449 lines checked

No code changed:

arch/x86/kernel/cpu/cyrix.o:

   text	   data	    bss	    dec	    hex	filename
   2048	    908	      4	   2960	    b90	cyrix.o.before
   2048	    908	      4	   2960	    b90	cyrix.o.after

md5:
   9add5e69dbd788f91ff24eea8462dad7  cyrix.o.before.asm
   9add5e69dbd788f91ff24eea8462dad7  cyrix.o.after.asm

Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Paolo Ciarrocchi 2008-02-22 23:11:23 +01:00 committed by Ingo Molnar
parent 7030760ae5
commit adf85265b4
1 changed files with 56 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

113
arch/x86/kernel/cpu/cyrix.c
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@ -19,7 +19,7 @@ static void __cpuinit do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
{ {
unsigned char ccr2, ccr3; unsigned char ccr2, ccr3;
unsigned long flags; unsigned long flags;
/* we test for DEVID by checking whether CCR3 is writable */ /* we test for DEVID by checking whether CCR3 is writable */
local_irq_save(flags); local_irq_save(flags);
ccr3 = getCx86(CX86_CCR3); ccr3 = getCx86(CX86_CCR3);
@ -37,8 +37,7 @@ static void __cpuinit do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
setCx86(CX86_CCR2, ccr2); setCx86(CX86_CCR2, ccr2);
*dir0 = 0xfe; *dir0 = 0xfe;
} }
} } else {
else {
setCx86(CX86_CCR3, ccr3); /* restore CCR3 */ setCx86(CX86_CCR3, ccr3); /* restore CCR3 */
/* read DIR0 and DIR1 CPU registers */ /* read DIR0 and DIR1 CPU registers */
@ -86,7 +85,7 @@ static char cyrix_model_mult2[] __cpuinitdata = "12233445";
static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c) static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c)
{ {
unsigned long flags; unsigned long flags;
if (Cx86_dir0_msb == 3) { if (Cx86_dir0_msb == 3) {
unsigned char ccr3, ccr5; unsigned char ccr3, ccr5;
@ -132,7 +131,7 @@ static void __cpuinit set_cx86_memwb(void)
/* set 'Not Write-through' */ /* set 'Not Write-through' */
write_cr0(read_cr0() | X86_CR0_NW); write_cr0(read_cr0() | X86_CR0_NW);
/* CCR2 bit 2: lock NW bit and set WT1 */ /* CCR2 bit 2: lock NW bit and set WT1 */
setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14 ); setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14);
} }
static void __cpuinit set_cx86_inc(void) static void __cpuinit set_cx86_inc(void)
@ -148,7 +147,7 @@ static void __cpuinit set_cx86_inc(void)
setCx86(CX86_PCR1, getCx86(CX86_PCR1) | 0x02); setCx86(CX86_PCR1, getCx86(CX86_PCR1) | 0x02);
/* PCR0 -- Performance Control */ /* PCR0 -- Performance Control */
/* Incrementor Margin 10 */ /* Incrementor Margin 10 */
setCx86(CX86_PCR0, getCx86(CX86_PCR0) | 0x04); setCx86(CX86_PCR0, getCx86(CX86_PCR0) | 0x04);
setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
} }
@ -167,16 +166,16 @@ static void __cpuinit geode_configure(void)
ccr3 = getCx86(CX86_CCR3); ccr3 = getCx86(CX86_CCR3);
setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
/* FPU fast, DTE cache, Mem bypass */ /* FPU fast, DTE cache, Mem bypass */
setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x38); setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x38);
setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
set_cx86_memwb(); set_cx86_memwb();
set_cx86_reorder(); set_cx86_reorder();
set_cx86_inc(); set_cx86_inc();
local_irq_restore(flags); local_irq_restore(flags);
} }
@ -187,12 +186,14 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
char *buf = c->x86_model_id; char *buf = c->x86_model_id;
const char *p = NULL; const char *p = NULL;
/* Bit 31 in normal CPUID used for nonstandard 3DNow ID; /*
3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */ * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
*/
clear_bit(0*32+31, c->x86_capability); clear_bit(0*32+31, c->x86_capability);
/* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */ /* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */
if ( test_bit(1*32+24, c->x86_capability) ) { if (test_bit(1*32+24, c->x86_capability)) {
clear_bit(1*32+24, c->x86_capability); clear_bit(1*32+24, c->x86_capability);
set_bit(X86_FEATURE_CXMMX, c->x86_capability); set_bit(X86_FEATURE_CXMMX, c->x86_capability);
} }
@ -213,7 +214,7 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
* the model, multiplier and stepping. Black magic included, * the model, multiplier and stepping. Black magic included,
* to make the silicon step/rev numbers match the printed ones. * to make the silicon step/rev numbers match the printed ones.
*/ */
switch (dir0_msn) { switch (dir0_msn) {
unsigned char tmp; unsigned char tmp;
@ -250,17 +251,18 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
{ {
u32 vendor, device; u32 vendor, device;
/* It isn't really a PCI quirk directly, but the cure is the /*
same. The MediaGX has deep magic SMM stuff that handles the * It isn't really a PCI quirk directly, but the cure is the
SB emulation. It throws away the fifo on disable_dma() which * same. The MediaGX has deep magic SMM stuff that handles the
is wrong and ruins the audio. * SB emulation. It throws away the fifo on disable_dma() which
* is wrong and ruins the audio.
Bug2: VSA1 has a wrap bug so that using maximum sized DMA *
causes bad things. According to NatSemi VSA2 has another * Bug2: VSA1 has a wrap bug so that using maximum sized DMA
bug to do with 'hlt'. I've not seen any boards using VSA2 * causes bad things. According to NatSemi VSA2 has another
and X doesn't seem to support it either so who cares 8). * bug to do with 'hlt'. I've not seen any boards using VSA2
VSA1 we work around however. * and X doesn't seem to support it either so who cares 8).
*/ * VSA1 we work around however.
*/
printk(KERN_INFO "Working around Cyrix MediaGX virtual DMA bugs.\n"); printk(KERN_INFO "Working around Cyrix MediaGX virtual DMA bugs.\n");
isa_dma_bridge_buggy = 2; isa_dma_bridge_buggy = 2;
@ -273,52 +275,48 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
/* /*
* The 5510/5520 companion chips have a funky PIT. * The 5510/5520 companion chips have a funky PIT.
*/ */
if (vendor == PCI_VENDOR_ID_CYRIX && if (vendor == PCI_VENDOR_ID_CYRIX &&
(device == PCI_DEVICE_ID_CYRIX_5510 || device == PCI_DEVICE_ID_CYRIX_5520)) (device == PCI_DEVICE_ID_CYRIX_5510 || device == PCI_DEVICE_ID_CYRIX_5520))
mark_tsc_unstable("cyrix 5510/5520 detected"); mark_tsc_unstable("cyrix 5510/5520 detected");
} }
#endif #endif
c->x86_cache_size=16; /* Yep 16K integrated cache thats it */ c->x86_cache_size = 16; /* Yep 16K integrated cache thats it */
/* GXm supports extended cpuid levels 'ala' AMD */ /* GXm supports extended cpuid levels 'ala' AMD */
if (c->cpuid_level == 2) { if (c->cpuid_level == 2) {
/* Enable cxMMX extensions (GX1 Datasheet 54) */ /* Enable cxMMX extensions (GX1 Datasheet 54) */
setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1); setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1);
/* /*
* GXm : 0x30 ... 0x5f GXm datasheet 51 * GXm : 0x30 ... 0x5f GXm datasheet 51
* GXlv: 0x6x GXlv datasheet 54 * GXlv: 0x6x GXlv datasheet 54
* ? : 0x7x * ? : 0x7x
* GX1 : 0x8x GX1 datasheet 56 * GX1 : 0x8x GX1 datasheet 56
*/ */
if((0x30 <= dir1 && dir1 <= 0x6f) || (0x80 <=dir1 && dir1 <= 0x8f)) if ((0x30 <= dir1 && dir1 <= 0x6f) || (0x80 <= dir1 && dir1 <= 0x8f))
geode_configure(); geode_configure();
get_model_name(c); /* get CPU marketing name */ get_model_name(c); /* get CPU marketing name */
return; return;
} } else { /* MediaGX */
else { /* MediaGX */
Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4'; Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
p = Cx86_cb+2; p = Cx86_cb+2;
c->x86_model = (dir1 & 0x20) ? 1 : 2; c->x86_model = (dir1 & 0x20) ? 1 : 2;
} }
break; break;
case 5: /* 6x86MX/M II */ case 5: /* 6x86MX/M II */
if (dir1 > 7) if (dir1 > 7) {
{
dir0_msn++; /* M II */ dir0_msn++; /* M II */
/* Enable MMX extensions (App note 108) */ /* Enable MMX extensions (App note 108) */
setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1); setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1);
} } else {
else
{
c->coma_bug = 1; /* 6x86MX, it has the bug. */ c->coma_bug = 1; /* 6x86MX, it has the bug. */
} }
tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0; tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0;
Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7]; Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7];
p = Cx86_cb+tmp; p = Cx86_cb+tmp;
if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20)) if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20))
(c->x86_model)++; (c->x86_model)++;
/* Emulate MTRRs using Cyrix's ARRs. */ /* Emulate MTRRs using Cyrix's ARRs. */
set_bit(X86_FEATURE_CYRIX_ARR, c->x86_capability); set_bit(X86_FEATURE_CYRIX_ARR, c->x86_capability);
@ -343,7 +341,8 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
break; break;
} }
strcpy(buf, Cx86_model[dir0_msn & 7]); strcpy(buf, Cx86_model[dir0_msn & 7]);
if (p) strcat(buf, p); if (p)
strcat(buf, p);
return; return;
} }
@ -352,7 +351,8 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
*/ */
static void __cpuinit init_nsc(struct cpuinfo_x86 *c) static void __cpuinit init_nsc(struct cpuinfo_x86 *c)
{ {
/* There may be GX1 processors in the wild that are branded /*
* There may be GX1 processors in the wild that are branded
* NSC and not Cyrix. * NSC and not Cyrix.
* *
* This function only handles the GX processor, and kicks every * This function only handles the GX processor, and kicks every
@ -377,7 +377,7 @@ static void __cpuinit init_nsc(struct cpuinfo_x86 *c)
* by the fact that they preserve the flags across the division of 5/2. * by the fact that they preserve the flags across the division of 5/2.
* PII and PPro exhibit this behavior too, but they have cpuid available. * PII and PPro exhibit this behavior too, but they have cpuid available.
*/ */
/* /*
* Perform the Cyrix 5/2 test. A Cyrix won't change * Perform the Cyrix 5/2 test. A Cyrix won't change
* the flags, while other 486 chips will. * the flags, while other 486 chips will.
@ -398,27 +398,26 @@ static inline int test_cyrix_52div(void)
return (unsigned char) (test >> 8) == 0x02; return (unsigned char) (test >> 8) == 0x02;
} }
static void __cpuinit cyrix_identify(struct cpuinfo_x86 * c) static void __cpuinit cyrix_identify(struct cpuinfo_x86 *c)
{ {
/* Detect Cyrix with disabled CPUID */ /* Detect Cyrix with disabled CPUID */
if ( c->x86 == 4 && test_cyrix_52div() ) { if (c->x86 == 4 && test_cyrix_52div()) {
unsigned char dir0, dir1; unsigned char dir0, dir1;
strcpy(c->x86_vendor_id, "CyrixInstead"); strcpy(c->x86_vendor_id, "CyrixInstead");
c->x86_vendor = X86_VENDOR_CYRIX; c->x86_vendor = X86_VENDOR_CYRIX;
/* Actually enable cpuid on the older cyrix */ /* Actually enable cpuid on the older cyrix */
/* Retrieve CPU revisions */ /* Retrieve CPU revisions */
do_cyrix_devid(&dir0, &dir1); do_cyrix_devid(&dir0, &dir1);
dir0>>=4; dir0 >>= 4;
/* Check it is an affected model */ /* Check it is an affected model */
if (dir0 == 5 || dir0 == 3) if (dir0 == 5 || dir0 == 3) {
{
unsigned char ccr3; unsigned char ccr3;
unsigned long flags; unsigned long flags;
printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n"); printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n");
@ -434,7 +433,7 @@ static void __cpuinit cyrix_identify(struct cpuinfo_x86 * c)
static struct cpu_dev cyrix_cpu_dev __cpuinitdata = { static struct cpu_dev cyrix_cpu_dev __cpuinitdata = {
.c_vendor = "Cyrix", .c_vendor = "Cyrix",
.c_ident = { "CyrixInstead" }, .c_ident = { "CyrixInstead" },
.c_init = init_cyrix, .c_init = init_cyrix,
.c_identify = cyrix_identify, .c_identify = cyrix_identify,
}; };
@ -443,7 +442,7 @@ cpu_vendor_dev_register(X86_VENDOR_CYRIX, &cyrix_cpu_dev);
static struct cpu_dev nsc_cpu_dev __cpuinitdata = { static struct cpu_dev nsc_cpu_dev __cpuinitdata = {
.c_vendor = "NSC", .c_vendor = "NSC",
.c_ident = { "Geode by NSC" }, .c_ident = { "Geode by NSC" },
.c_init = init_nsc, .c_init = init_nsc,
}; };