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octeontx2-af: cn10k: Set cache lines for NPA batch alloc 

Set NPA batch allocation engine to process 35 cache lines
per turn on CN10k platform.

Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Geetha sowjanya 2021-08-25 11:05:03 +05:30 committed by David S. Miller
parent 87e5ef4b19
commit ae2c341eb0
3 changed files with 13 additions and 0 deletions
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1
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
View File

@ -594,6 +594,7 @@ struct npa_lf_alloc_rsp {
u32 stack_pg_ptrs; /* No of ptrs per stack page */
u32 stack_pg_bytes; /* Size of stack page */
u16 qints; /* NPA_AF_CONST::QINTS */
u8 cache_lines; /*BATCH ALLOC DMA */
};
/* NPA AQ enqueue msg */

11
drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c
View File

@ -419,6 +419,10 @@ int rvu_mbox_handler_npa_lf_alloc(struct rvu *rvu,
rsp->stack_pg_ptrs = (cfg >> 8) & 0xFF;
rsp->stack_pg_bytes = cfg & 0xFF;
rsp->qints = (cfg >> 28) & 0xFFF;
if (!is_rvu_otx2(rvu)) {
cfg = rvu_read64(rvu, block->addr, NPA_AF_BATCH_CTL);
rsp->cache_lines = (cfg >> 1) & 0x3F;
}
return rc;
}
@ -478,6 +482,13 @@ static int npa_aq_init(struct rvu *rvu, struct rvu_block *block)
#endif
rvu_write64(rvu, block->addr, NPA_AF_NDC_CFG, cfg);
/* For CN10K NPA BATCH DMA set 35 cache lines */
if (!is_rvu_otx2(rvu)) {
cfg = rvu_read64(rvu, block->addr, NPA_AF_BATCH_CTL);
cfg &= ~0x7EULL;
cfg |= BIT_ULL(6) | BIT_ULL(2) | BIT_ULL(1);
rvu_write64(rvu, block->addr, NPA_AF_BATCH_CTL, cfg);
}
/* Result structure can be followed by Aura/Pool context at
* RES + 128bytes and a write mask at RES + 256 bytes, depending on
* operation type. Alloc sufficient result memory for all operations.

1
drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
View File

@ -156,6 +156,7 @@
#define NPA_AF_AQ_DONE_INT_W1S (0x0688)
#define NPA_AF_AQ_DONE_ENA_W1S (0x0690)
#define NPA_AF_AQ_DONE_ENA_W1C (0x0698)
#define NPA_AF_BATCH_CTL (0x06a0)
#define NPA_AF_LFX_AURAS_CFG(a) (0x4000 | (a) << 18)
#define NPA_AF_LFX_LOC_AURAS_BASE(a) (0x4010 | (a) << 18)
#define NPA_AF_LFX_QINTS_CFG(a) (0x4100 | (a) << 18)