mirror of https://gitee.com/openkylin/linux.git
MIPS: traps: Add CPU PM callback for trap configuration
Implement a CPU power management callback for restoring trap related CPU configuration after CPU power up from a low power state. The following state is restored: - Status register - HWREna register - Exception vector configuration registers - Context/XContext register Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
This commit is contained in:
James Hogan
Paul Burton
parent
b1d4c6cac0
commit
ae4ce45419
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@ -31,11 +31,15 @@ do { \
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} while (0)
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#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
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#define TLBMISS_HANDLER_RESTORE() \
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write_c0_xcontext((unsigned long) smp_processor_id() << \
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SMP_CPUID_REGSHIFT)
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#define TLBMISS_HANDLER_SETUP() \
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do { \
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TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
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write_c0_xcontext((unsigned long) smp_processor_id() << \
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SMP_CPUID_REGSHIFT); \
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TLBMISS_HANDLER_RESTORE(); \
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} while (0)
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#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
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@ -47,9 +51,12 @@ do { \
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*/
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extern unsigned long pgd_current[];
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#define TLBMISS_HANDLER_SETUP() \
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#define TLBMISS_HANDLER_RESTORE() \
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write_c0_context((unsigned long) smp_processor_id() << \
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SMP_CPUID_REGSHIFT); \
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SMP_CPUID_REGSHIFT)
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#define TLBMISS_HANDLER_SETUP() \
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TLBMISS_HANDLER_RESTORE(); \
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back_to_back_c0_hazard(); \
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TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
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#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
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@ -15,6 +15,7 @@
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#include <linux/bug.h>
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#include <linux/compiler.h>
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#include <linux/context_tracking.h>
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#include <linux/cpu_pm.h>
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#include <linux/kexec.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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@ -1865,32 +1866,16 @@ static int __init ulri_disable(char *s)
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}
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__setup("noulri", ulri_disable);
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void per_cpu_trap_init(bool is_boot_cpu)
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/* configure STATUS register */
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static void configure_status(void)
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{
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unsigned int cpu = smp_processor_id();
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unsigned int status_set = ST0_CU0;
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unsigned int hwrena = cpu_hwrena_impl_bits;
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#ifdef CONFIG_MIPS_MT_SMTC
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int secondaryTC = 0;
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int bootTC = (cpu == 0);
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/*
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* Only do per_cpu_trap_init() for first TC of Each VPE.
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* Note that this hack assumes that the SMTC init code
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* assigns TCs consecutively and in ascending order.
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*/
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if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
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((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
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secondaryTC = 1;
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#endif /* CONFIG_MIPS_MT_SMTC */
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/*
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* Disable coprocessors and select 32-bit or 64-bit addressing
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* and the 16/32 or 32/32 FPR register model. Reset the BEV
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* flag that some firmware may have left set and the TS bit (for
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* IP27). Set XX for ISA IV code to work.
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*/
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unsigned int status_set = ST0_CU0;
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#ifdef CONFIG_64BIT
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status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
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#endif
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@ -1901,6 +1886,12 @@ void per_cpu_trap_init(bool is_boot_cpu)
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change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
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status_set);
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}
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/* configure HWRENA register */
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static void configure_hwrena(void)
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{
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unsigned int hwrena = cpu_hwrena_impl_bits;
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if (cpu_has_mips_r2)
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hwrena |= 0x0000000f;
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@ -1910,11 +1901,10 @@ void per_cpu_trap_init(bool is_boot_cpu)
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if (hwrena)
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write_c0_hwrena(hwrena);
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}
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#ifdef CONFIG_MIPS_MT_SMTC
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if (!secondaryTC) {
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#endif /* CONFIG_MIPS_MT_SMTC */
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static void configure_exception_vector(void)
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{
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if (cpu_has_veic || cpu_has_vint) {
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unsigned long sr = set_c0_status(ST0_BEV);
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write_c0_ebase(ebase);
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@ -1930,6 +1920,34 @@ void per_cpu_trap_init(bool is_boot_cpu)
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} else
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set_c0_cause(CAUSEF_IV);
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}
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}
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void per_cpu_trap_init(bool is_boot_cpu)
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{
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unsigned int cpu = smp_processor_id();
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#ifdef CONFIG_MIPS_MT_SMTC
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int secondaryTC = 0;
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int bootTC = (cpu == 0);
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/*
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* Only do per_cpu_trap_init() for first TC of Each VPE.
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* Note that this hack assumes that the SMTC init code
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* assigns TCs consecutively and in ascending order.
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*/
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if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
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((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
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secondaryTC = 1;
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#endif /* CONFIG_MIPS_MT_SMTC */
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configure_status();
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configure_hwrena();
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#ifdef CONFIG_MIPS_MT_SMTC
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if (!secondaryTC) {
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#endif /* CONFIG_MIPS_MT_SMTC */
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configure_exception_vector();
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/*
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* Before R2 both interrupt numbers were fixed to 7, so on R2 only:
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@ -2185,3 +2203,32 @@ void __init trap_init(void)
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cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
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}
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static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
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void *v)
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{
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switch (cmd) {
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case CPU_PM_ENTER_FAILED:
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case CPU_PM_EXIT:
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configure_status();
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configure_hwrena();
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configure_exception_vector();
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/* Restore register with CPU number for TLB handlers */
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TLBMISS_HANDLER_RESTORE();
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block trap_pm_notifier_block = {
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.notifier_call = trap_pm_notifier,
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};
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static int __init trap_pm_init(void)
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{
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return cpu_pm_register_notifier(&trap_pm_notifier_block);
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}
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arch_initcall(trap_pm_init);
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