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Renesas ARM-based SoC bockw board updates for v3.10 

Add SMSC ethernet support to the bockw board.
 
 This pull request is based on a merge of:
 git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-soc-r8a7778-for-v3.10
 git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-boards3-for-v3.10
 
 The reason for merging with renesas-soc-r8a7778-for-v3.10 is
 to provide pre-requisite SoC code to configure IRQ pins for the
 SMSC ethernet.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.12 (GNU/Linux)
 
 iQIcBAABAgAGBQJRXjzZAAoJENfPZGlqN0++PfsP+wXKEGnS47efqfh/wgNQTiJP
 bc7ottBOfXkiLhz1NB3LMw1c9mNF+n57wetiED9l0BR8gwGi7X6Fespa024lIp32
 Sw/FSHnAdUwB7MD+uQUrDeN2+UUplR+0aSY7vmcAQ7XHbuytB1BylQrA2sxQA1NY
 O27J5s6IjZNWSX2FzUPmEygDhUcikkAPbC6IfmfEIJPoLJ9Li6NePsuPc2sXokby
 kJkbqhnL20Ja9Vv8aKuSJO/4IYQHCkk0jAvaJRDctlWHMlPEBqsx7DXFRSmzTc7F
 Wm4uySM1VrVpCoGDkQtd+zbatVJOOuKzq0kN5g0LDe73hpHrQx8pJyFdZtxPD9BA
 ctm3E+p6Wx8Zna2WtQgsNRjkRPCz5kcwqCdmnCLykOTtxs8lwnRUn3nN3qL0R+uu
 KeIRsxwgL9O67FyrZk4WW9On0Qob2vd66ktCF12FCTlX3vYIQR0vFAQ8VlF2OeZl
 S2VJ6+FM8N5jUzDFoOzYTUOXcskomUxPop93HbRDho/bgLhOba9cD9tSep/4p7ZZ
 s4oz20WSBUvszK7He8kGiTn8vwR/1mEwQPyP1eZh/hSxWGxdqdTQ5ZcT4IA0Hbe9
 CFZ9qiRBzOjBhDEgYmKYo3BN9Yk7WVB9ILWa7xsD05yskcaA+ps/Om0/81i75iCx
 n1PDVuc/A9H1F5REQaM7
 =kjpJ
 -----END PGP SIGNATURE-----

Merge tag 'renesas-boards-bockw-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards2

From Simon Horman <horms+renesas@verge.net.au>:

Renesas ARM-based SoC bockw board updates for v3.10

Add SMSC ethernet support to the bockw board.

This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-soc-r8a7778-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-boards3-for-v3.10

The reason for merging with renesas-soc-r8a7778-for-v3.10 is
to provide pre-requisite SoC code to configure IRQ pins for the
SMSC ethernet.

* tag 'renesas-boards-bockw-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: bockw: enable network settings on bootargs
  ARM: shmobile: bockw: add SMSC ethernet support

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2013-04-09 14:45:09 +02:00
parent f12d9f9c9b 446ee9b2d8
commit afa3a13da7
6 changed files with 114 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/r8a7778-bockw.dts
View File

@ -22,7 +22,7 @@ / {
compatible = "renesas,bockw", "renesas,r8a7778";
chosen {
bootargs = "console=ttySC0,115200 ignore_loglevel";
bootargs = "console=ttySC0,115200 ignore_loglevel ip=dhcp root=/dev/nfs";
};
memory {

1
arch/arm/mach-shmobile/Kconfig
View File

@ -133,6 +133,7 @@ config MACH_BOCKW
bool "BOCK-W platform"
depends on ARCH_R8A7778
select ARCH_REQUIRE_GPIOLIB
select RENESAS_INTC_IRQPIN
select USE_OF
config MACH_MARZEN

38
arch/arm/mach-shmobile/board-bockw.c
View File

@ -19,14 +19,52 @@
*/
#include <linux/platform_device.h>
#include <linux/smsc911x.h>
#include <mach/common.h>
#include <mach/irqs.h>
#include <mach/r8a7778.h>
#include <asm/mach/arch.h>
static struct smsc911x_platform_config smsc911x_data = {
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
.flags = SMSC911X_USE_32BIT,
.phy_interface = PHY_INTERFACE_MODE_MII,
};
static struct resource smsc911x_resources[] = {
DEFINE_RES_MEM(0x18300000, 0x1000),
DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */
};
#define IRQ0MR 0x30
static void __init bockw_init(void)
{
void __iomem *fpga;
r8a7778_clock_init();
r8a7778_init_irq_extpin(1);
r8a7778_add_standard_devices();
fpga = ioremap_nocache(0x18200000, SZ_1M);
if (fpga) {
/*
* CAUTION
*
* IRQ0/1 is cascaded interrupt from FPGA.
* it should be cared in the future
* Now, it is assuming IRQ0 was used only from SMSC.
*/
u16 val = ioread16(fpga + IRQ0MR);
val &= ~(1 << 4); /* enable SMSC911x */
iowrite16(val, fpga + IRQ0MR);
iounmap(fpga);
platform_device_register_resndata(
&platform_bus, "smsc911x", -1,
smsc911x_resources, ARRAY_SIZE(smsc911x_resources),
&smsc911x_data, sizeof(smsc911x_data));
}
}
static const char *bockw_boards_compat_dt[] __initdata = {

3
arch/arm/mach-shmobile/clock-r8a7778.c
View File

@ -58,11 +58,13 @@ static struct clk *main_clks[] = {
};
enum {
MSTP114,
MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
MSTP016, MSTP015,
MSTP_NR };
static struct clk mstp_clks[MSTP_NR] = {
[MSTP114] = SH_CLK_MSTP32(&clkp, MSTPCR1, 14, 0), /* Ether */
[MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */
[MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */
[MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */
@ -75,6 +77,7 @@ static struct clk mstp_clks[MSTP_NR] = {
static struct clk_lookup lookups[] = {
/* MSTP32 clocks */
CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */

4
arch/arm/mach-shmobile/include/mach/r8a7778.h
View File

@ -18,11 +18,15 @@
#ifndef __ASM_R8A7778_H__
#define __ASM_R8A7778_H__
#include <linux/sh_eth.h>
extern void r8a7778_add_standard_devices(void);
extern void r8a7778_add_standard_devices_dt(void);
extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata);
extern void r8a7778_init_delay(void);
extern void r8a7778_init_irq(void);
extern void r8a7778_init_irq_dt(void);
extern void r8a7778_clock_init(void);
extern void r8a7778_init_irq_extpin(int irlm);
#endif /* __ASM_R8A7778_H__ */

83
arch/arm/mach-shmobile/setup-r8a7778.c
View File

@ -3,6 +3,7 @@
*
* Copyright (C) 2013 Renesas Solutions Corp.
* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
* Copyright (C) 2013 Cogent Embedded, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -23,6 +24,7 @@
#include <linux/irqchip/arm-gic.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_data/irq-renesas-intc-irqpin.h>
#include <linux/platform_device.h>
#include <linux/irqchip.h>
#include <linux/serial_sci.h>
@ -78,22 +80,20 @@ static struct sh_timer_config sh_tmu1_platform_data = {
.clocksource_rating = 200,
};
#define PLATFORM_INFO(n, i) \
{ \
.parent = &platform_bus, \
.name = #n, \
.id = i, \
.res = n ## i ## _resources, \
.num_res = ARRAY_SIZE(n ## i ##_resources), \
.data = &n ## i ##_platform_data, \
.size_data = sizeof(n ## i ## _platform_data), \
}
struct platform_device_info platform_devinfo[] = {
PLATFORM_INFO(sh_tmu, 0),
PLATFORM_INFO(sh_tmu, 1),
/* Ether */
static struct resource ether_resources[] = {
DEFINE_RES_MEM(0xfde00000, 0x400),
DEFINE_RES_IRQ(gic_iid(0x89)),
};
#define r8a7778_register_tmu(idx) \
platform_device_register_resndata( \
&platform_bus, "sh_tmu", idx, \
sh_tmu##idx##_resources, \
ARRAY_SIZE(sh_tmu##idx##_resources), \
&sh_tmu##idx##_platform_data, \
sizeof(sh_tmu##idx##_platform_data))
void __init r8a7778_add_standard_devices(void)
{
int i;
@ -114,8 +114,59 @@ void __init r8a7778_add_standard_devices(void)
&scif_platform_data[i],
sizeof(struct plat_sci_port));
for (i = 0; i < ARRAY_SIZE(platform_devinfo); i++)
platform_device_register_full(&platform_devinfo[i]);
r8a7778_register_tmu(0);
r8a7778_register_tmu(1);
}
void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
{
platform_device_register_resndata(&platform_bus, "sh_eth", -1,
ether_resources,
ARRAY_SIZE(ether_resources),
pdata, sizeof(*pdata));
}
static struct renesas_intc_irqpin_config irqpin_platform_data = {
.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
.sense_bitfield_width = 2,
};
static struct resource irqpin_resources[] = {
DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */
DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */
DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */
DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
};
void __init r8a7778_init_irq_extpin(int irlm)
{
void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
unsigned long tmp;
if (!icr0) {
pr_warn("r8a7778: unable to setup external irq pin mode\n");
return;
}
tmp = ioread32(icr0);
if (irlm)
tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
else
tmp &= ~(1 << 23); /* IRL mode - not supported */
tmp |= (1 << 21); /* LVLMODE = 1 */
iowrite32(tmp, icr0);
iounmap(icr0);
if (irlm)
platform_device_register_resndata(
&platform_bus, "renesas_intc_irqpin", -1,
irqpin_resources, ARRAY_SIZE(irqpin_resources),
&irqpin_platform_data, sizeof(irqpin_platform_data));
}
#define INT2SMSKCR0 0x82288 /* 0xfe782288 */