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ath9k: Fix PLL powersave for AR9485 

Use the value in ah->config.pll_pwrsave to determine
which array needs to be loaded. Also, initialize
pll_pwrsave to 1 by default.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
This commit is contained in:
Sujith Manoharan 2015-03-09 14:20:07 +05:30 committed by Kalle Valo
parent e519f78f11
commit afa7e6dbd9
3 changed files with 13 additions and 7 deletions
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10
drivers/net/wireless/ath/ath9k/ar9003_hw.c
View File

@ -195,16 +195,16 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
INIT_INI_ARRAY(&ah->iniCckfirJapan2484, INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
ar9485_1_1_baseband_core_txfir_coeff_japan_2484); ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
if (ah->config.no_pll_pwrsave) { if (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) {
INIT_INI_ARRAY(&ah->iniPcieSerdes, INIT_INI_ARRAY(&ah->iniPcieSerdes,
ar9485_1_1_pcie_phy_clkreq_disable_L1); ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
ar9485_1_1_pcie_phy_clkreq_disable_L1); ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
} else { } else {
INIT_INI_ARRAY(&ah->iniPcieSerdes, INIT_INI_ARRAY(&ah->iniPcieSerdes,
ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1); ar9485_1_1_pcie_phy_clkreq_disable_L1);
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1); ar9485_1_1_pcie_phy_clkreq_disable_L1);
} }
} else if (AR_SREV_9462_21(ah)) { } else if (AR_SREV_9462_21(ah)) {
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],

2
drivers/net/wireless/ath/ath9k/hw.h
View File

@ -341,7 +341,7 @@ struct ath9k_ops_config {
u32 ant_ctrl_comm2g_switch_enable; u32 ant_ctrl_comm2g_switch_enable;
bool xatten_margin_cfg; bool xatten_margin_cfg;
bool alt_mingainidx; bool alt_mingainidx;
bool no_pll_pwrsave; bool pll_pwrsave;
bool tx_gain_buffalo; bool tx_gain_buffalo;
bool led_active_high; bool led_active_high;
}; };

8
drivers/net/wireless/ath/ath9k/init.c
View File

@ -437,8 +437,14 @@ static void ath9k_init_pcoem_platform(struct ath_softc *sc)
ath_info(common, "Enable WAR for ASPM D3/L1\n"); ath_info(common, "Enable WAR for ASPM D3/L1\n");
} }
/*
* The default value of pll_pwrsave is 1.
* For certain AR9485 cards, it is set to 0.
*/
ah->config.pll_pwrsave = 1;
if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) { if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
ah->config.no_pll_pwrsave = true; ah->config.pll_pwrsave = 0;
ath_info(common, "Disable PLL PowerSave\n"); ath_info(common, "Disable PLL PowerSave\n");
} }