mirror of https://gitee.com/openkylin/linux.git
drm/amd/display: call set_mpc_output_csc from hwsequencer
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yue Hin Lau
Alex Deucher
parent
96b8af6eb4
commit
afbeb2638b
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@ -117,6 +117,33 @@ static const struct dcn10_input_csc_matrix dcn10_input_csc_matrix[] = {
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0x2568, 0x43ee, 0xdbb2} }
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};
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struct output_csc_matrix {
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enum dc_color_space color_space;
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uint16_t regval[12];
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};
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static const struct output_csc_matrix output_csc_matrix[] = {
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{ COLOR_SPACE_SRGB,
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{ 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
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{ COLOR_SPACE_SRGB_LIMITED,
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{ 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} },
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{ COLOR_SPACE_YCBCR601,
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{ 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47,
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0xF6B9, 0xE00, 0x1000} },
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{ COLOR_SPACE_YCBCR709,
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{ 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA,
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0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
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/* TODO: correct values below */
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{ COLOR_SPACE_YCBCR601_LIMITED,
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{ 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
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0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} },
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{ COLOR_SPACE_YCBCR709_LIMITED,
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{ 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
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0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
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{ COLOR_SPACE_UNKNOWN,
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }
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};
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static void program_gamut_remap(
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@ -223,68 +250,6 @@ void dpp1_cm_set_gamut_remap(
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}
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}
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void dpp1_cm_set_output_csc_default(
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struct dpp *dpp_base,
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enum dc_color_space colorspace)
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{
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struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
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uint32_t ocsc_mode = 0;
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switch (colorspace) {
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case COLOR_SPACE_SRGB:
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case COLOR_SPACE_2020_RGB_FULLRANGE:
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ocsc_mode = 0;
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break;
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case COLOR_SPACE_SRGB_LIMITED:
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case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
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ocsc_mode = 1;
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break;
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case COLOR_SPACE_YCBCR601:
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case COLOR_SPACE_YCBCR601_LIMITED:
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ocsc_mode = 2;
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break;
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case COLOR_SPACE_YCBCR709:
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case COLOR_SPACE_YCBCR709_LIMITED:
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case COLOR_SPACE_2020_YCBCR:
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ocsc_mode = 3;
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break;
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case COLOR_SPACE_UNKNOWN:
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default:
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break;
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}
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REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
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}
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static void dpp1_cm_get_reg_field(
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struct dcn10_dpp *dpp,
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struct xfer_func_reg *reg)
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{
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reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
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reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
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reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
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reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
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reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
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reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
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reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
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reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
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reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B;
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reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B;
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reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;
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reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;
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reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;
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reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;
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reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
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reg->masks.field_region_linear_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
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reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B;
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reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B;
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reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
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reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
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}
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static void dpp1_cm_program_color_matrix(
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struct dcn10_dpp *dpp,
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const struct out_csc_color_matrix *tbl_entry)
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@ -326,6 +291,57 @@ static void dpp1_cm_program_color_matrix(
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}
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}
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void dpp1_cm_set_output_csc_default(
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struct dpp *dpp_base,
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enum dc_color_space colorspace)
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{
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struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
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struct out_csc_color_matrix tbl_entry;
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int i, j;
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int arr_size = sizeof(output_csc_matrix) / sizeof(struct output_csc_matrix);
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uint32_t ocsc_mode = 4;
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tbl_entry.color_space = colorspace;
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for (i = 0; i < arr_size; i++)
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if (output_csc_matrix[i].color_space == colorspace) {
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for (j = 0; j < 12; j++)
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tbl_entry.regval[j] = output_csc_matrix[i].regval[j];
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break;
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}
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REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
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dpp1_cm_program_color_matrix(dpp, &tbl_entry);
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}
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static void dpp1_cm_get_reg_field(
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struct dcn10_dpp *dpp,
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struct xfer_func_reg *reg)
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{
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reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
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reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
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reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
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reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
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reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
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reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
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reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
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reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
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reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B;
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reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B;
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reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;
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reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;
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reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;
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reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;
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reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
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reg->masks.field_region_linear_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
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reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B;
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reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B;
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reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
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reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
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}
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void dpp1_cm_set_output_csc_adjustment(
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struct dpp *dpp_base,
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const struct out_csc_color_matrix *tbl_entry)
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@ -1666,12 +1666,68 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
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tbl_entry.color_space = color_space;
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//tbl_entry.regval = matrix;
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if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
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pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry);
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} else {
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if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
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pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
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}
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}
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//program ocsc matrix for dcn 2
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static void set_mpc_output_csc(struct dc *dc,
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struct pipe_ctx *pipe_ctx,
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enum dc_color_space colorspace,
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uint16_t *matrix,
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int opp_id)
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{
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struct mpc *mpc = dc->res_pool->mpc;
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int i;
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struct out_csc_color_matrix tbl_entry;
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enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
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if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
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//uint16_t matrix[12];
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for (i = 0; i < 12; i++)
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tbl_entry.regval[i] = matrix[i];
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tbl_entry.color_space = colorspace;
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if (mpc->funcs->set_output_csc != NULL)
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mpc->funcs->set_output_csc(mpc,
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opp_id,
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&tbl_entry,
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ocsc_mode);
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}
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else {
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if (mpc->funcs->set_ocsc_default != NULL)
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mpc->funcs->set_ocsc_default(mpc,
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opp_id,
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colorspace,
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ocsc_mode);
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}
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}
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static void program_output_csc(struct dc *dc,
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struct pipe_ctx *pipe_ctx,
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enum dc_color_space colorspace,
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uint16_t *matrix,
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int opp_id)
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{
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if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
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program_csc_matrix(pipe_ctx,
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colorspace,
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matrix);
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else
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set_mpc_output_csc(dc,
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pipe_ctx,
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colorspace,
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matrix,
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opp_id);
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}
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static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
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{
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if (pipe_ctx->plane_state->visible)
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@ -1909,10 +1965,11 @@ static void update_dchubp_dpp(
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/*gamut remap*/
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program_gamut_remap(pipe_ctx);
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program_csc_matrix(pipe_ctx,
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program_output_csc(dc,
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pipe_ctx,
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pipe_ctx->stream->output_color_space,
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pipe_ctx->stream->csc_color_matrix.matrix);
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pipe_ctx->stream->csc_color_matrix.matrix,
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mpcc_cfg.opp_id);
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hubp->funcs->hubp_program_surface_config(
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hubp,
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@ -28,6 +28,12 @@
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#include "dc_hw_types.h"
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#include "opp.h"
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enum mpc_output_csc_mode {
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MPC_OUTPUT_CSC_DISABLE = 0,
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MPC_OUTPUT_CSC_COEF_A,
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MPC_OUTPUT_CSC_COEF_B
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};
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struct mpcc_cfg {
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int dpp_id;
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int opp_id;
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@ -58,6 +64,16 @@ struct mpc_funcs {
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int (*get_opp_id)(struct mpc *mpc, int mpcc_id);
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void (*set_output_csc)(struct mpc *mpc,
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int opp_id,
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const struct out_csc_color_matrix *tbl_entry,
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enum mpc_output_csc_mode ocsc_mode);
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void (*set_ocsc_default)(struct mpc *mpc,
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int opp_id,
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enum dc_color_space color_space,
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enum mpc_output_csc_mode ocsc_mode);
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};
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#endif
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