mirror of https://gitee.com/openkylin/linux.git
perf/x86/intel: Set PERF_ATTACH_SCHED_CB for large PEBS and LBR
To supply a PID/TID for large PEBS, it requires flushing the PEBS buffer
in a context switch.
For normal LBRs, a context switch can flip the address space and LBR
entries are not tagged with an identifier, we need to wipe the LBR, even
for per-cpu events.
For LBR callstack, save/restore the stack is required during a context
switch.
Set PERF_ATTACH_SCHED_CB for the event with large PEBS & LBR.
Fixes: 9c964efa43
("perf/x86/intel: Drain the PEBS buffer during context switches")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lkml.kernel.org/r/20201130193842.10569-2-kan.liang@linux.intel.com
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@ -3662,8 +3662,10 @@ static int intel_pmu_hw_config(struct perf_event *event)
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if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
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if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
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event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
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event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
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if (!(event->attr.sample_type &
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if (!(event->attr.sample_type &
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~intel_pmu_large_pebs_flags(event)))
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~intel_pmu_large_pebs_flags(event))) {
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event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
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event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
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event->attach_state |= PERF_ATTACH_SCHED_CB;
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}
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}
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}
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if (x86_pmu.pebs_aliases)
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if (x86_pmu.pebs_aliases)
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x86_pmu.pebs_aliases(event);
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x86_pmu.pebs_aliases(event);
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@ -3676,6 +3678,7 @@ static int intel_pmu_hw_config(struct perf_event *event)
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ret = intel_pmu_setup_lbr_filter(event);
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ret = intel_pmu_setup_lbr_filter(event);
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if (ret)
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if (ret)
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return ret;
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return ret;
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event->attach_state |= PERF_ATTACH_SCHED_CB;
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/*
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/*
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* BTS is set up earlier in this path, so don't account twice
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* BTS is set up earlier in this path, so don't account twice
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