mirror of https://gitee.com/openkylin/linux.git
pinctrl: imx: add imx7ulp driver
i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 ports and IOMUXC DDR for DDR interface. This patch adds the IOMUXC1 support for A7. It only supports generic pin config. Cc: Bai Ping <ping.bai@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Dong Aisheng
Linus Walleij
parent
fc4f351a63
commit
b026402b73
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@ -103,6 +103,13 @@ config PINCTRL_IMX7D
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help
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Say Y here to enable the imx7d pinctrl driver
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config PINCTRL_IMX7ULP
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bool "IMX7ULP pinctrl driver"
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depends on SOC_IMX7ULP
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select PINCTRL_IMX
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help
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Say Y here to enable the imx7ulp pinctrl driver
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config PINCTRL_VF610
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bool "Freescale Vybrid VF610 pinctrl driver"
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depends on SOC_VF610
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@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
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obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
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obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
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obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
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obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
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obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
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obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
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obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
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@ -0,0 +1,338 @@
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright (C) 2017 NXP
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*
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* Author: Dong Aisheng <aisheng.dong@nxp.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-imx.h"
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enum imx7ulp_pads {
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IMX7ULP_PAD_PTC0 = 0,
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IMX7ULP_PAD_PTC1,
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IMX7ULP_PAD_PTC2,
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IMX7ULP_PAD_PTC3,
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IMX7ULP_PAD_PTC4,
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IMX7ULP_PAD_PTC5,
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IMX7ULP_PAD_PTC6,
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IMX7ULP_PAD_PTC7,
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IMX7ULP_PAD_PTC8,
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IMX7ULP_PAD_PTC9,
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IMX7ULP_PAD_PTC10,
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IMX7ULP_PAD_PTC11,
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IMX7ULP_PAD_PTC12,
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IMX7ULP_PAD_PTC13,
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IMX7ULP_PAD_PTC14,
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IMX7ULP_PAD_PTC15,
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IMX7ULP_PAD_PTC16,
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IMX7ULP_PAD_PTC17,
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IMX7ULP_PAD_PTC18,
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IMX7ULP_PAD_PTC19,
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IMX7ULP_PAD_RESERVE0,
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IMX7ULP_PAD_RESERVE1,
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IMX7ULP_PAD_RESERVE2,
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IMX7ULP_PAD_RESERVE3,
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IMX7ULP_PAD_RESERVE4,
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IMX7ULP_PAD_RESERVE5,
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IMX7ULP_PAD_RESERVE6,
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IMX7ULP_PAD_RESERVE7,
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IMX7ULP_PAD_RESERVE8,
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IMX7ULP_PAD_RESERVE9,
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IMX7ULP_PAD_RESERVE10,
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IMX7ULP_PAD_RESERVE11,
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IMX7ULP_PAD_PTD0,
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IMX7ULP_PAD_PTD1,
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IMX7ULP_PAD_PTD2,
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IMX7ULP_PAD_PTD3,
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IMX7ULP_PAD_PTD4,
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IMX7ULP_PAD_PTD5,
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IMX7ULP_PAD_PTD6,
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IMX7ULP_PAD_PTD7,
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IMX7ULP_PAD_PTD8,
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IMX7ULP_PAD_PTD9,
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IMX7ULP_PAD_PTD10,
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IMX7ULP_PAD_PTD11,
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IMX7ULP_PAD_RESERVE12,
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IMX7ULP_PAD_RESERVE13,
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IMX7ULP_PAD_RESERVE14,
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IMX7ULP_PAD_RESERVE15,
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IMX7ULP_PAD_RESERVE16,
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IMX7ULP_PAD_RESERVE17,
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IMX7ULP_PAD_RESERVE18,
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IMX7ULP_PAD_RESERVE19,
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IMX7ULP_PAD_RESERVE20,
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IMX7ULP_PAD_RESERVE21,
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IMX7ULP_PAD_RESERVE22,
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IMX7ULP_PAD_RESERVE23,
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IMX7ULP_PAD_RESERVE24,
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IMX7ULP_PAD_RESERVE25,
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IMX7ULP_PAD_RESERVE26,
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IMX7ULP_PAD_RESERVE27,
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IMX7ULP_PAD_RESERVE28,
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IMX7ULP_PAD_RESERVE29,
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IMX7ULP_PAD_RESERVE30,
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IMX7ULP_PAD_RESERVE31,
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IMX7ULP_PAD_PTE0,
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IMX7ULP_PAD_PTE1,
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IMX7ULP_PAD_PTE2,
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IMX7ULP_PAD_PTE3,
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IMX7ULP_PAD_PTE4,
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IMX7ULP_PAD_PTE5,
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IMX7ULP_PAD_PTE6,
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IMX7ULP_PAD_PTE7,
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IMX7ULP_PAD_PTE8,
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IMX7ULP_PAD_PTE9,
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IMX7ULP_PAD_PTE10,
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IMX7ULP_PAD_PTE11,
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IMX7ULP_PAD_PTE12,
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IMX7ULP_PAD_PTE13,
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IMX7ULP_PAD_PTE14,
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IMX7ULP_PAD_PTE15,
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IMX7ULP_PAD_RESERVE32,
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IMX7ULP_PAD_RESERVE33,
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IMX7ULP_PAD_RESERVE34,
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IMX7ULP_PAD_RESERVE35,
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IMX7ULP_PAD_RESERVE36,
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IMX7ULP_PAD_RESERVE37,
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IMX7ULP_PAD_RESERVE38,
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IMX7ULP_PAD_RESERVE39,
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IMX7ULP_PAD_RESERVE40,
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IMX7ULP_PAD_RESERVE41,
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IMX7ULP_PAD_RESERVE42,
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IMX7ULP_PAD_RESERVE43,
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IMX7ULP_PAD_RESERVE44,
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IMX7ULP_PAD_RESERVE45,
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IMX7ULP_PAD_RESERVE46,
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IMX7ULP_PAD_RESERVE47,
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IMX7ULP_PAD_PTF0,
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IMX7ULP_PAD_PTF1,
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IMX7ULP_PAD_PTF2,
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IMX7ULP_PAD_PTF3,
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IMX7ULP_PAD_PTF4,
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IMX7ULP_PAD_PTF5,
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IMX7ULP_PAD_PTF6,
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IMX7ULP_PAD_PTF7,
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IMX7ULP_PAD_PTF8,
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IMX7ULP_PAD_PTF9,
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IMX7ULP_PAD_PTF10,
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IMX7ULP_PAD_PTF11,
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IMX7ULP_PAD_PTF12,
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IMX7ULP_PAD_PTF13,
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IMX7ULP_PAD_PTF14,
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IMX7ULP_PAD_PTF15,
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IMX7ULP_PAD_PTF16,
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IMX7ULP_PAD_PTF17,
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IMX7ULP_PAD_PTF18,
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IMX7ULP_PAD_PTF19,
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};
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/* Pad names for the pinmux subsystem */
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static const struct pinctrl_pin_desc imx7ulp_pinctrl_pads[] = {
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC0),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC1),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC2),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC3),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC4),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC5),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC6),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC7),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC8),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC9),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC10),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC11),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC12),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC13),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC14),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC15),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC16),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC17),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC18),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC19),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE0),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE1),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE2),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE3),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE4),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE5),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE6),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE7),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE8),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE9),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE10),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE11),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD0),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD1),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD2),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD3),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD4),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD5),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD6),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD7),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD8),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD9),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD10),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD11),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE12),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE13),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE14),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE15),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE16),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE17),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE18),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE19),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE20),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE21),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE22),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE23),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE24),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE25),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE26),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE27),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE28),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE29),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE30),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE31),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE0),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE1),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE2),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE3),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE4),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE5),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE6),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE7),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE8),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE9),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE10),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE11),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE12),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE13),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE14),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE15),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE32),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE33),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE34),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE35),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE36),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE37),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE38),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE39),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE40),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE41),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE42),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE43),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE44),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE45),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE46),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE47),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF0),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF1),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF2),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF3),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF4),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF5),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF6),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF7),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF8),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF9),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF10),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF11),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF12),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF13),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF14),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF15),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF16),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF17),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF18),
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF19),
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};
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#define BM_LK_ENABLED BIT(15)
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#define BM_MUX_MODE 0xf00
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#define BP_MUX_MODE 8
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#define BM_PULL_ENABLED BIT(1)
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struct imx_cfg_params_decode imx7ulp_cfg_decodes[] = {
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IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_STRENGTH, BIT(6), 6),
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IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_PUSH_PULL, BIT(5), 5),
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IMX_CFG_PARAMS_DECODE(PIN_CONFIG_SLEW_RATE, BIT(2), 2),
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IMX_CFG_PARAMS_DECODE(PIN_CONFIG_BIAS_DISABLE, BIT(1), 1),
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IMX_CFG_PARAMS_DECODE(PIN_CONFIG_BIAS_PULL_UP, BIT(0), 0),
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IMX_CFG_PARAMS_DECODE_INVERT(PIN_CONFIG_DRIVE_OPEN_DRAIN, BIT(5), 5),
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IMX_CFG_PARAMS_DECODE_INVERT(PIN_CONFIG_BIAS_PULL_DOWN, BIT(0), 0),
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};
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static void imx7ulp_cfg_params_fixup(unsigned long *configs,
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unsigned int num_configs,
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u32 *raw_config)
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{
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enum pin_config_param param;
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u32 param_val;
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int i;
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/* lock field disabled */
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*raw_config &= ~BM_LK_ENABLED;
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for (i = 0; i < num_configs; i++) {
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param = pinconf_to_config_param(configs[i]);
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param_val = pinconf_to_config_argument(configs[i]);
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if ((param == PIN_CONFIG_BIAS_PULL_UP) ||
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(param == PIN_CONFIG_BIAS_PULL_DOWN)) {
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/* pull enabled */
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*raw_config |= BM_PULL_ENABLED;
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return;
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}
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}
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}
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static struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = {
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.pins = imx7ulp_pinctrl_pads,
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.npins = ARRAY_SIZE(imx7ulp_pinctrl_pads),
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.flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
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.mux_mask = BM_MUX_MODE,
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.mux_shift = BP_MUX_MODE,
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.generic_pinconf = true,
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.decodes = imx7ulp_cfg_decodes,
|
||||
.num_decodes = ARRAY_SIZE(imx7ulp_cfg_decodes),
|
||||
.fixup = imx7ulp_cfg_params_fixup,
|
||||
};
|
||||
|
||||
static const struct of_device_id imx7ulp_pinctrl_of_match[] = {
|
||||
{ .compatible = "fsl,imx7ulp-iomuxc1", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int imx7ulp_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return imx_pinctrl_probe(pdev, &imx7ulp_pinctrl_info);
|
||||
}
|
||||
|
||||
static struct platform_driver imx7ulp_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "imx7ulp-pinctrl",
|
||||
.of_match_table = of_match_ptr(imx7ulp_pinctrl_of_match),
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = imx7ulp_pinctrl_probe,
|
||||
};
|
||||
|
||||
static int __init imx7ulp_pinctrl_init(void)
|
||||
{
|
||||
return platform_driver_register(&imx7ulp_pinctrl_driver);
|
||||
}
|
||||
arch_initcall(imx7ulp_pinctrl_init);
|
||||
Loading…
Reference in New Issue