mirror of https://gitee.com/openkylin/linux.git
net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
cxgb4 Ethernet driver now queries PCIe configuration space to determine if it can send TLPs to it with the Relaxed Ordering Attribute set. Remove the enable_pcie_relaxed_ordering() to avoid enable PCIe Capability Device Control[Relaxed Ordering Enable] at probe routine, to make sure the driver will not send the Relaxed Ordering TLPs to the Root Complex which could not deal the Relaxed Ordering TLPs. Signed-off-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> Reviewed-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -529,6 +529,7 @@ enum { /* adapter flags */
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USING_SOFT_PARAMS = (1 << 6),
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MASTER_PF = (1 << 7),
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FW_OFLD_CONN = (1 << 9),
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ROOT_NO_RELAXED_ORDERING = (1 << 10),
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};
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enum {
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@ -4654,11 +4654,6 @@ static void print_port_info(const struct net_device *dev)
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dev->name, adap->params.vpd.id, adap->name, buf);
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}
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static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
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{
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pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
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}
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/*
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* Free the following resources:
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* - memory used for tables
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@ -4908,7 +4903,6 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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}
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pci_enable_pcie_error_reporting(pdev);
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enable_pcie_relaxed_ordering(pdev);
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pci_set_master(pdev);
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pci_save_state(pdev);
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@ -4947,6 +4941,23 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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adapter->msg_enable = DFLT_MSG_ENABLE;
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memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
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/* If possible, we use PCIe Relaxed Ordering Attribute to deliver
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* Ingress Packet Data to Free List Buffers in order to allow for
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* chipset performance optimizations between the Root Complex and
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* Memory Controllers. (Messages to the associated Ingress Queue
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* notifying new Packet Placement in the Free Lists Buffers will be
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* send without the Relaxed Ordering Attribute thus guaranteeing that
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* all preceding PCIe Transaction Layer Packets will be processed
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* first.) But some Root Complexes have various issues with Upstream
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* Transaction Layer Packets with the Relaxed Ordering Attribute set.
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* The PCIe devices which under the Root Complexes will be cleared the
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* Relaxed Ordering bit in the configuration space, So we check our
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* PCIe configuration space to see if it's flagged with advice against
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* using Relaxed Ordering.
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*/
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if (!pcie_relaxed_ordering_enabled(pdev))
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adapter->flags |= ROOT_NO_RELAXED_ORDERING;
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spin_lock_init(&adapter->stats_lock);
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spin_lock_init(&adapter->tid_release_lock);
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spin_lock_init(&adapter->win0_lock);
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@ -2719,6 +2719,7 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
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struct fw_iq_cmd c;
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struct sge *s = &adap->sge;
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struct port_info *pi = netdev_priv(dev);
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int relaxed = !(adap->flags & ROOT_NO_RELAXED_ORDERING);
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/* Size needs to be multiple of 16, including status entry. */
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iq->size = roundup(iq->size, 16);
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@ -2772,8 +2773,8 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
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flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc);
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c.iqns_to_fl0congen |= htonl(FW_IQ_CMD_FL0PACKEN_F |
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FW_IQ_CMD_FL0FETCHRO_F |
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FW_IQ_CMD_FL0DATARO_F |
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FW_IQ_CMD_FL0FETCHRO_V(relaxed) |
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FW_IQ_CMD_FL0DATARO_V(relaxed) |
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FW_IQ_CMD_FL0PADEN_F);
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if (cong >= 0)
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c.iqns_to_fl0congen |=
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