mirror of https://gitee.com/openkylin/linux.git
The second batch of clk driver code for -rc1
- A handful of fixes for lmk04832 driver - Migrate the basic clk divider to use determine rate ops - Fix modpost build for hisilicon hi3559a driver - Actually set the parent in k210_clk_set_parent() -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmDmPo0RHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSW+UA/+ID512DVohpldBQ9FPmGJ88SV/wr3fpp1 pbJC6f3Kwc7pWS913Glj31xpRHtOMOZLbRvFIa2xBuIuP4sWu3QTAdDk9tf8/5hE 8S7dAKwXoy2n6jVCB87sMXF+Gyd6vzU0KIdjTLX0UuF+U/scejjYAc7j8pQZ3X85 LWb6+F4B8VQAIwExkiuDlxaaOEs0bJ6fDsj0lpFDivF7feLYmFLAO7gNIIOlQyqb 3yY8o+dviUoGGplSU0YS9dlkCFMef4LxonqyvoVWOq6d2N3mx16gmKgdR4lpQndl oqoA11WPC+kmozwlG0g6g2YyZN8KOSUCgXDSm6vFB79BfR3QNv9tjNY4ybGQs1yF DX21n5tb5FKxXNIGWrYQAXjdMuqByCGCZCTDMWdnDx/zawTD507HCEnpQ7okSlOt gGsntJFeCwVn9CftmdWnRj5hp88DBa2Fu1GUmRJ86J+BMSte0QBaS5jvEnVt7kRl YjI1+eM2pqCqUCxY6MpQvoqvnOf3KOb3kxwuieWuZgIbnig9iN//1I0K4b4XJ1tH sTsUtdGxqp/asn0oMfGCurJry2iKZRaAG9XcEaUS2Mji4rvhXn02VSCvXq45iq8J efZg6rBnpIxZygfUiSAxgKZNRIS2bnOjNWj8BDBB3dcX/H9x17XTu+irJbRjNUEQ BXEgGmWMH+Q= =Tk4i -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull more clk updates from Stephen Boyd: - A handful of fixes for lmk04832 driver - Migrate the basic clk divider to use determine rate ops - Fix modpost build for hisilicon hi3559a driver - Actually set the parent in k210_clk_set_parent() * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: Revert "clk: divider: Switch from .round_rate to .determine_rate by default" clk: hisilicon: hi3559a: Drop __init markings everywhere clk: meson: regmap: switch to determine_rate for the dividers clk: divider: Switch from .round_rate to .determine_rate by default clk: divider: Add re-usable determine_rate implementations clk: k210: Fix k210_clk_set_parent() clk: lmk04832: Fix spelling mistakes in dev_err messages and comments clk: lmk04832: fix return value check in lmk04832_probe() clk: stm32mp1: fix missing spin_lock_init()
This commit is contained in:
Linus Torvalds
commit
b0dfd9af28
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@ -343,16 +343,63 @@ static int clk_divider_bestdiv(struct clk_hw *hw, struct clk_hw *parent,
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return bestdiv;
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}
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int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
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const struct clk_div_table *table, u8 width,
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unsigned long flags)
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{
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int div;
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div = clk_divider_bestdiv(hw, req->best_parent_hw, req->rate,
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&req->best_parent_rate, table, width, flags);
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req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
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return 0;
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}
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EXPORT_SYMBOL_GPL(divider_determine_rate);
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int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
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const struct clk_div_table *table, u8 width,
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unsigned long flags, unsigned int val)
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{
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int div;
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div = _get_div(table, val, flags, width);
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/* Even a read-only clock can propagate a rate change */
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
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if (!req->best_parent_hw)
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return -EINVAL;
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req->best_parent_rate = clk_hw_round_rate(req->best_parent_hw,
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req->rate * div);
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}
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req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
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return 0;
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}
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EXPORT_SYMBOL_GPL(divider_ro_determine_rate);
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long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
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unsigned long rate, unsigned long *prate,
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const struct clk_div_table *table,
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u8 width, unsigned long flags)
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{
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int div;
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struct clk_rate_request req = {
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.rate = rate,
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.best_parent_rate = *prate,
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.best_parent_hw = parent,
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};
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int ret;
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div = clk_divider_bestdiv(hw, parent, rate, prate, table, width, flags);
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ret = divider_determine_rate(hw, &req, table, width, flags);
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if (ret)
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return ret;
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return DIV_ROUND_UP_ULL((u64)*prate, div);
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*prate = req.best_parent_rate;
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return req.rate;
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}
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EXPORT_SYMBOL_GPL(divider_round_rate_parent);
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@ -361,23 +408,23 @@ long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
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const struct clk_div_table *table, u8 width,
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unsigned long flags, unsigned int val)
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{
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int div;
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struct clk_rate_request req = {
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.rate = rate,
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.best_parent_rate = *prate,
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.best_parent_hw = parent,
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};
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int ret;
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div = _get_div(table, val, flags, width);
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ret = divider_ro_determine_rate(hw, &req, table, width, flags, val);
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if (ret)
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return ret;
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/* Even a read-only clock can propagate a rate change */
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
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if (!parent)
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return -EINVAL;
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*prate = req.best_parent_rate;
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*prate = clk_hw_round_rate(parent, rate * div);
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}
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return DIV_ROUND_UP_ULL((u64)*prate, div);
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return req.rate;
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}
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EXPORT_SYMBOL_GPL(divider_ro_round_rate_parent);
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static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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@ -722,6 +722,7 @@ static int k210_clk_set_parent(struct clk_hw *hw, u8 index)
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reg |= BIT(cfg->mux_bit);
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else
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reg &= ~BIT(cfg->mux_bit);
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writel(reg, ksc->regs + cfg->mux_reg);
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spin_unlock_irqrestore(&ksc->clk_lock, flags);
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return 0;
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@ -519,7 +519,7 @@ static long lmk04832_vco_round_rate(struct clk_hw *hw, unsigned long rate,
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vco_rate = lmk04832_calc_pll2_params(*prate, rate, &n, &p, &r);
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if (vco_rate < 0) {
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dev_err(lmk->dev, "PLL2 parmeters out of range\n");
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dev_err(lmk->dev, "PLL2 parameters out of range\n");
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return vco_rate;
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}
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@ -550,7 +550,7 @@ static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
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vco_rate = lmk04832_calc_pll2_params(prate, rate, &n, &p, &r);
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if (vco_rate < 0) {
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dev_err(lmk->dev, "failed to determine PLL2 parmeters\n");
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dev_err(lmk->dev, "failed to determine PLL2 parameters\n");
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return vco_rate;
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}
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@ -573,7 +573,7 @@ static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
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/*
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* PLL2_N registers must be programmed after other PLL2 dividers are
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* programed to ensure proper VCO frequency calibration
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* programmed to ensure proper VCO frequency calibration
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*/
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ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0,
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FIELD_GET(0x030000, n));
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@ -1120,7 +1120,7 @@ static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
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return -EINVAL;
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}
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/* Enable Duty Cycle Corretion */
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/* Enable Duty Cycle Correction */
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if (dclk_div == 1) {
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ret = regmap_update_bits(lmk->regmap,
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LMK04832_REG_CLKOUT_CTRL3(dclk->id),
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@ -1425,23 +1425,23 @@ static int lmk04832_probe(struct spi_device *spi)
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lmk->dclk = devm_kcalloc(lmk->dev, info->num_channels >> 1,
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sizeof(struct lmk_dclk), GFP_KERNEL);
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if (IS_ERR(lmk->dclk)) {
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ret = PTR_ERR(lmk->dclk);
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if (!lmk->dclk) {
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ret = -ENOMEM;
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goto err_disable_oscin;
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}
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lmk->clkout = devm_kcalloc(lmk->dev, info->num_channels,
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sizeof(*lmk->clkout), GFP_KERNEL);
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if (IS_ERR(lmk->clkout)) {
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ret = PTR_ERR(lmk->clkout);
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if (!lmk->clkout) {
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ret = -ENOMEM;
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goto err_disable_oscin;
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}
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lmk->clk_data = devm_kzalloc(lmk->dev, struct_size(lmk->clk_data, hws,
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info->num_channels),
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GFP_KERNEL);
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if (IS_ERR(lmk->clk_data)) {
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ret = PTR_ERR(lmk->clk_data);
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if (!lmk->clk_data) {
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ret = -ENOMEM;
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goto err_disable_oscin;
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}
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@ -2263,6 +2263,7 @@ static int stm32_rcc_reset_init(struct device *dev, void __iomem *base,
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if (!reset_data)
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return -ENOMEM;
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spin_lock_init(&reset_data->lock);
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reset_data->membase = base;
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reset_data->rcdev.owner = THIS_MODULE;
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reset_data->rcdev.ops = &stm32_reset_ops;
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@ -107,25 +107,25 @@ static const struct hisi_fixed_rate_clock hi3559av100_fixed_rate_clks_crg[] = {
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};
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static const char *fmc_mux_p[] __initconst = {
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static const char *fmc_mux_p[] = {
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"24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m"
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};
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static const char *mmc_mux_p[] __initconst = {
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static const char *mmc_mux_p[] = {
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"100k", "25m", "49p5m", "99m", "187p5m", "150m", "198m", "400k"
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};
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static const char *sysapb_mux_p[] __initconst = {
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static const char *sysapb_mux_p[] = {
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"24m", "50m",
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};
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static const char *sysbus_mux_p[] __initconst = {
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static const char *sysbus_mux_p[] = {
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"24m", "300m"
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};
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static const char *uart_mux_p[] __initconst = { "50m", "24m", "3m" };
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static const char *uart_mux_p[] = { "50m", "24m", "3m" };
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static const char *a73_clksel_mux_p[] __initconst = {
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static const char *a73_clksel_mux_p[] = {
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"24m", "apll", "1000m"
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};
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@ -136,7 +136,7 @@ static const u32 sysbus_mux_table[] = { 0, 1 };
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static const u32 uart_mux_table[] = { 0, 1, 2 };
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static const u32 a73_clksel_mux_table[] = { 0, 1, 2 };
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static struct hisi_mux_clock hi3559av100_mux_clks_crg[] __initdata = {
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static struct hisi_mux_clock hi3559av100_mux_clks_crg[] = {
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{
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HI3559AV100_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
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CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table,
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@ -181,7 +181,7 @@ static struct hisi_mux_clock hi3559av100_mux_clks_crg[] __initdata = {
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},
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};
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static struct hisi_gate_clock hi3559av100_gate_clks[] __initdata = {
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static struct hisi_gate_clock hi3559av100_gate_clks[] = {
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{
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HI3559AV100_FMC_CLK, "clk_fmc", "fmc_mux",
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CLK_SET_RATE_PARENT, 0x170, 1, 0,
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@ -336,7 +336,7 @@ static struct hisi_gate_clock hi3559av100_gate_clks[] __initdata = {
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},
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};
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static struct hi3559av100_pll_clock hi3559av100_pll_clks[] __initdata = {
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static struct hi3559av100_pll_clock hi3559av100_pll_clks[] = {
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{
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HI3559AV100_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3,
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0x4, 0, 12, 12, 6
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@ -502,7 +502,7 @@ static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
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}
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}
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static __init struct hisi_clock_data *hi3559av100_clk_register(
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static struct hisi_clock_data *hi3559av100_clk_register(
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struct platform_device *pdev)
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{
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struct hisi_clock_data *clk_data;
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@ -549,7 +549,7 @@ static __init struct hisi_clock_data *hi3559av100_clk_register(
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return ERR_PTR(ret);
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}
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static __init void hi3559av100_clk_unregister(struct platform_device *pdev)
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static void hi3559av100_clk_unregister(struct platform_device *pdev)
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{
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struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
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@ -568,8 +568,7 @@ static const struct hisi_crg_funcs hi3559av100_crg_funcs = {
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.unregister_clks = hi3559av100_clk_unregister,
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};
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static struct hisi_fixed_rate_clock hi3559av100_shub_fixed_rate_clks[]
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__initdata = {
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static struct hisi_fixed_rate_clock hi3559av100_shub_fixed_rate_clks[] = {
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{ HI3559AV100_SHUB_SOURCE_SOC_24M, "clk_source_24M", NULL, 0, 24000000UL, },
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{ HI3559AV100_SHUB_SOURCE_SOC_200M, "clk_source_200M", NULL, 0, 200000000UL, },
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{ HI3559AV100_SHUB_SOURCE_SOC_300M, "clk_source_300M", NULL, 0, 300000000UL, },
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@ -587,16 +586,16 @@ static struct hisi_fixed_rate_clock hi3559av100_shub_fixed_rate_clks[]
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/* shub mux clk */
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static u32 shub_source_clk_mux_table[] = {0, 1, 2, 3};
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static const char *shub_source_clk_mux_p[] __initconst = {
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static const char *shub_source_clk_mux_p[] = {
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"clk_source_24M", "clk_source_200M", "clk_source_300M", "clk_source_PLL"
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};
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static u32 shub_uart_source_clk_mux_table[] = {0, 1, 2, 3};
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static const char *shub_uart_source_clk_mux_p[] __initconst = {
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||||
static const char *shub_uart_source_clk_mux_p[] = {
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"clk_uart_32K", "clk_uart_div_clk", "clk_uart_div_clk", "clk_source_24M"
|
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};
|
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|
||||
static struct hisi_mux_clock hi3559av100_shub_mux_clks[] __initdata = {
|
||||
static struct hisi_mux_clock hi3559av100_shub_mux_clks[] = {
|
||||
{
|
||||
HI3559AV100_SHUB_SOURCE_CLK, "shub_clk", shub_source_clk_mux_p,
|
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ARRAY_SIZE(shub_source_clk_mux_p),
|
||||
|
|
@ -615,7 +614,7 @@ static struct hisi_mux_clock hi3559av100_shub_mux_clks[] __initdata = {
|
|||
static struct clk_div_table shub_spi_clk_table[] = {{0, 8}, {1, 4}, {2, 2}};
|
||||
static struct clk_div_table shub_uart_div_clk_table[] = {{1, 8}, {2, 4}};
|
||||
|
||||
static struct hisi_divider_clock hi3559av100_shub_div_clks[] __initdata = {
|
||||
static struct hisi_divider_clock hi3559av100_shub_div_clks[] = {
|
||||
{ HI3559AV100_SHUB_SPI_SOURCE_CLK, "clk_spi_clk", "shub_clk", 0, 0x20, 24, 2,
|
||||
CLK_DIVIDER_ALLOW_ZERO, shub_spi_clk_table,
|
||||
},
|
||||
|
|
@ -625,7 +624,7 @@ static struct hisi_divider_clock hi3559av100_shub_div_clks[] __initdata = {
|
|||
};
|
||||
|
||||
/* shub gate clk */
|
||||
static struct hisi_gate_clock hi3559av100_shub_gate_clks[] __initdata = {
|
||||
static struct hisi_gate_clock hi3559av100_shub_gate_clks[] = {
|
||||
{
|
||||
HI3559AV100_SHUB_SPI0_CLK, "clk_shub_spi0", "clk_spi_clk",
|
||||
0, 0x20, 1, 0,
|
||||
|
|
@ -697,7 +696,7 @@ static int hi3559av100_shub_default_clk_set(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static __init struct hisi_clock_data *hi3559av100_shub_clk_register(
|
||||
static struct hisi_clock_data *hi3559av100_shub_clk_register(
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct hisi_clock_data *clk_data = NULL;
|
||||
|
|
@ -751,7 +750,7 @@ static __init struct hisi_clock_data *hi3559av100_shub_clk_register(
|
|||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
static __init void hi3559av100_shub_clk_unregister(struct platform_device *pdev)
|
||||
static void hi3559av100_shub_clk_unregister(struct platform_device *pdev)
|
||||
{
|
||||
struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
|
||||
|
||||
|
|
|
|||
|
|
@ -75,8 +75,8 @@ static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw,
|
|||
div->width);
|
||||
}
|
||||
|
||||
static long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
static int clk_regmap_div_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct clk_regmap *clk = to_clk_regmap(hw);
|
||||
struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk);
|
||||
|
|
@ -87,18 +87,17 @@ static long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate,
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if (div->flags & CLK_DIVIDER_READ_ONLY) {
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||||
ret = regmap_read(clk->map, div->offset, &val);
|
||||
if (ret)
|
||||
/* Gives a hint that something is wrong */
|
||||
return 0;
|
||||
return ret;
|
||||
|
||||
val >>= div->shift;
|
||||
val &= clk_div_mask(div->width);
|
||||
|
||||
return divider_ro_round_rate(hw, rate, prate, div->table,
|
||||
div->width, div->flags, val);
|
||||
return divider_ro_determine_rate(hw, req, div->table,
|
||||
div->width, div->flags, val);
|
||||
}
|
||||
|
||||
return divider_round_rate(hw, rate, prate, div->table, div->width,
|
||||
div->flags);
|
||||
return divider_determine_rate(hw, req, div->table, div->width,
|
||||
div->flags);
|
||||
}
|
||||
|
||||
static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
|
@ -123,14 +122,14 @@ static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
|
||||
const struct clk_ops clk_regmap_divider_ops = {
|
||||
.recalc_rate = clk_regmap_div_recalc_rate,
|
||||
.round_rate = clk_regmap_div_round_rate,
|
||||
.determine_rate = clk_regmap_div_determine_rate,
|
||||
.set_rate = clk_regmap_div_set_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_regmap_divider_ops);
|
||||
|
||||
const struct clk_ops clk_regmap_divider_ro_ops = {
|
||||
.recalc_rate = clk_regmap_div_recalc_rate,
|
||||
.round_rate = clk_regmap_div_round_rate,
|
||||
.determine_rate = clk_regmap_div_determine_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_regmap_divider_ro_ops);
|
||||
|
||||
|
|
|
|||
|
|
@ -629,6 +629,12 @@ long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
|
|||
unsigned long rate, unsigned long *prate,
|
||||
const struct clk_div_table *table, u8 width,
|
||||
unsigned long flags, unsigned int val);
|
||||
int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
|
||||
const struct clk_div_table *table, u8 width,
|
||||
unsigned long flags);
|
||||
int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
|
||||
const struct clk_div_table *table, u8 width,
|
||||
unsigned long flags, unsigned int val);
|
||||
int divider_get_val(unsigned long rate, unsigned long parent_rate,
|
||||
const struct clk_div_table *table, u8 width,
|
||||
unsigned long flags);
|
||||
|
|
|
|||
Loading…
Reference in New Issue