mirror of https://gitee.com/openkylin/linux.git
drm/nouveau/gk20a: reclocking support
Add support for reclocking on GK20A, using a statically-defined pstates table. The algorithms for calculating the coefficients and setting the clocks are directly taken from the ChromeOS kernel. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Alexandre Courbot
Ben Skeggs
parent
bb4d29df5e
commit
b13a0a9e29
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@ -65,6 +65,7 @@ nouveau-y += core/subdev/clock/nva3.o
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nouveau-y += core/subdev/clock/nvaa.o
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nouveau-y += core/subdev/clock/nvc0.o
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nouveau-y += core/subdev/clock/nve0.o
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nouveau-y += core/subdev/clock/gk20a.o
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nouveau-y += core/subdev/clock/pllnv04.o
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nouveau-y += core/subdev/clock/pllnva3.o
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nouveau-y += core/subdev/devinit/base.o
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@ -158,6 +158,7 @@ nve0_identify(struct nouveau_device *device)
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break;
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case 0xea:
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device->cname = "GK20A";
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device->oclass[NVDEV_SUBDEV_CLOCK ] = &gk20a_clock_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
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device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
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@ -147,6 +147,7 @@ extern struct nouveau_oclass *nvaa_clock_oclass;
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extern struct nouveau_oclass nva3_clock_oclass;
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extern struct nouveau_oclass nvc0_clock_oclass;
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extern struct nouveau_oclass nve0_clock_oclass;
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extern struct nouveau_oclass gk20a_clock_oclass;
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int nv04_clock_pll_set(struct nouveau_clock *, u32 type, u32 freq);
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int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
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@ -22,6 +22,7 @@
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#include <linux/log2.h>
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#include <linux/pm_runtime.h>
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#include <linux/power_supply.h>
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#include <linux/clk.h>
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#include <asm/unaligned.h>
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@ -0,0 +1,665 @@
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/*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c
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*
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*/
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#define MHZ (1000 * 1000)
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#define MASK(w) ((1 << w) - 1)
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#define SYS_GPCPLL_CFG_BASE 0x00137000
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#define GPC_BCASE_GPCPLL_CFG_BASE 0x00132800
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#define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0)
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#define GPCPLL_CFG_ENABLE BIT(0)
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#define GPCPLL_CFG_IDDQ BIT(1)
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#define GPCPLL_CFG_LOCK_DET_OFF BIT(4)
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#define GPCPLL_CFG_LOCK BIT(17)
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#define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4)
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#define GPCPLL_COEFF_M_SHIFT 0
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#define GPCPLL_COEFF_M_WIDTH 8
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#define GPCPLL_COEFF_N_SHIFT 8
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#define GPCPLL_COEFF_N_WIDTH 8
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#define GPCPLL_COEFF_P_SHIFT 16
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#define GPCPLL_COEFF_P_WIDTH 6
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#define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc)
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#define GPCPLL_CFG2_SETUP2_SHIFT 16
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#define GPCPLL_CFG2_PLL_STEPA_SHIFT 24
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#define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18)
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#define GPCPLL_CFG3_PLL_STEPB_SHIFT 16
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#define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c)
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#define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 0
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#define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8
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#define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 16
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#define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 22
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#define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 31
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#define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100)
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#define SEL_VCO_GPC2CLK_OUT_SHIFT 0
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#define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250)
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#define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1
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#define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31
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#define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1
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#define GPC2CLK_OUT_VCODIV_WIDTH 6
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#define GPC2CLK_OUT_VCODIV_SHIFT 8
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#define GPC2CLK_OUT_VCODIV1 0
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#define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \
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GPC2CLK_OUT_VCODIV_SHIFT)
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#define GPC2CLK_OUT_BYPDIV_WIDTH 6
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#define GPC2CLK_OUT_BYPDIV_SHIFT 0
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#define GPC2CLK_OUT_BYPDIV31 0x3c
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#define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \
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GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\
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| (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\
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| (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT))
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#define GPC2CLK_OUT_INIT_VAL ((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \
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GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \
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| (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \
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| (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT))
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#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG (GPC_BCASE_GPCPLL_CFG_BASE + 0xa0)
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#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 24
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#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \
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(0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT)
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#include <subdev/clock.h>
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#include <subdev/timer.h>
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#ifdef __KERNEL__
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#include <nouveau_platform.h>
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#endif
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static const u8 pl_to_div[] = {
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/* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
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/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32,
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};
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/* All frequencies in Mhz */
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struct gk20a_clk_pllg_params {
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u32 min_vco, max_vco;
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u32 min_u, max_u;
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u32 min_m, max_m;
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u32 min_n, max_n;
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u32 min_pl, max_pl;
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};
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static const struct gk20a_clk_pllg_params gk20a_pllg_params = {
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.min_vco = 1000, .max_vco = 1700,
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.min_u = 12, .max_u = 38,
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.min_m = 1, .max_m = 255,
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.min_n = 8, .max_n = 255,
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.min_pl = 1, .max_pl = 32,
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};
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struct gk20a_clock_priv {
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struct nouveau_clock base;
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const struct gk20a_clk_pllg_params *params;
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u32 m, n, pl;
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u32 parent_rate;
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};
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#define to_gk20a_clock(base) container_of(base, struct gk20a_clock_priv, base)
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static void
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gk20a_pllg_read_mnp(struct gk20a_clock_priv *priv)
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{
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u32 val;
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val = nv_rd32(priv, GPCPLL_COEFF);
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priv->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
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priv->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH);
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priv->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
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}
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static u32
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gk20a_pllg_calc_rate(struct gk20a_clock_priv *priv)
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{
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u32 rate;
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u32 divider;
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rate = priv->parent_rate * priv->n;
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divider = priv->m * pl_to_div[priv->pl];
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do_div(rate, divider);
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return rate / 2;
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}
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static int
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gk20a_pllg_calc_mnp(struct gk20a_clock_priv *priv, unsigned long rate)
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{
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u32 target_clk_f, ref_clk_f, target_freq;
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u32 min_vco_f, max_vco_f;
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u32 low_pl, high_pl, best_pl;
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u32 target_vco_f, vco_f;
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u32 best_m, best_n;
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u32 u_f;
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u32 m, n, n2;
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u32 delta, lwv, best_delta = ~0;
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u32 pl;
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target_clk_f = rate * 2 / MHZ;
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ref_clk_f = priv->parent_rate / MHZ;
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max_vco_f = priv->params->max_vco;
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min_vco_f = priv->params->min_vco;
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best_m = priv->params->max_m;
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best_n = priv->params->min_n;
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best_pl = priv->params->min_pl;
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target_vco_f = target_clk_f + target_clk_f / 50;
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if (max_vco_f < target_vco_f)
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max_vco_f = target_vco_f;
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/* min_pl <= high_pl <= max_pl */
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high_pl = (max_vco_f + target_vco_f - 1) / target_vco_f;
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high_pl = min(high_pl, priv->params->max_pl);
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high_pl = max(high_pl, priv->params->min_pl);
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/* min_pl <= low_pl <= max_pl */
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low_pl = min_vco_f / target_vco_f;
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low_pl = min(low_pl, priv->params->max_pl);
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low_pl = max(low_pl, priv->params->min_pl);
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/* Find Indices of high_pl and low_pl */
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for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) {
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if (pl_to_div[pl] >= low_pl) {
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low_pl = pl;
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break;
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}
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}
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for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) {
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if (pl_to_div[pl] >= high_pl) {
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high_pl = pl;
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break;
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}
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}
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nv_debug(priv, "low_PL %d(div%d), high_PL %d(div%d)", low_pl,
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pl_to_div[low_pl], high_pl, pl_to_div[high_pl]);
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/* Select lowest possible VCO */
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for (pl = low_pl; pl <= high_pl; pl++) {
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target_vco_f = target_clk_f * pl_to_div[pl];
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for (m = priv->params->min_m; m <= priv->params->max_m; m++) {
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u_f = ref_clk_f / m;
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if (u_f < priv->params->min_u)
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break;
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if (u_f > priv->params->max_u)
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continue;
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n = (target_vco_f * m) / ref_clk_f;
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n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f;
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if (n > priv->params->max_n)
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break;
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for (; n <= n2; n++) {
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if (n < priv->params->min_n)
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continue;
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if (n > priv->params->max_n)
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break;
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vco_f = ref_clk_f * n / m;
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if (vco_f >= min_vco_f && vco_f <= max_vco_f) {
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lwv = (vco_f + (pl_to_div[pl] / 2))
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/ pl_to_div[pl];
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delta = abs(lwv - target_clk_f);
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if (delta < best_delta) {
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best_delta = delta;
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best_m = m;
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best_n = n;
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best_pl = pl;
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if (best_delta == 0)
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goto found_match;
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}
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}
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}
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}
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}
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found_match:
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WARN_ON(best_delta == ~0);
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if (best_delta != 0)
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nv_debug(priv, "no best match for target @ %dMHz on gpc_pll",
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target_clk_f);
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priv->m = best_m;
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priv->n = best_n;
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priv->pl = best_pl;
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target_freq = gk20a_pllg_calc_rate(priv) / MHZ;
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nv_debug(priv, "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n",
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target_freq, priv->m, priv->n, priv->pl, pl_to_div[priv->pl]);
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return 0;
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}
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static int
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gk20a_pllg_slide(struct gk20a_clock_priv *priv, u32 n)
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{
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u32 val;
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int ramp_timeout;
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/* get old coefficients */
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val = nv_rd32(priv, GPCPLL_COEFF);
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/* do nothing if NDIV is the same */
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if (n == ((val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH)))
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return 0;
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/* setup */
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nv_mask(priv, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT,
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0x2b << GPCPLL_CFG2_PLL_STEPA_SHIFT);
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nv_mask(priv, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT,
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0xb << GPCPLL_CFG3_PLL_STEPB_SHIFT);
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/* pll slowdown mode */
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nv_mask(priv, GPCPLL_NDIV_SLOWDOWN,
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BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT),
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BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT));
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/* new ndiv ready for ramp */
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val = nv_rd32(priv, GPCPLL_COEFF);
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val &= ~(MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT);
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val |= (n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT;
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udelay(1);
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nv_wr32(priv, GPCPLL_COEFF, val);
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/* dynamic ramp to new ndiv */
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val = nv_rd32(priv, GPCPLL_NDIV_SLOWDOWN);
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val |= 0x1 << GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT;
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udelay(1);
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nv_wr32(priv, GPCPLL_NDIV_SLOWDOWN, val);
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for (ramp_timeout = 500; ramp_timeout > 0; ramp_timeout--) {
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udelay(1);
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val = nv_rd32(priv, GPC_BCAST_NDIV_SLOWDOWN_DEBUG);
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if (val & GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK)
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break;
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}
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/* exit slowdown mode */
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nv_mask(priv, GPCPLL_NDIV_SLOWDOWN,
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BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) |
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BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0);
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nv_rd32(priv, GPCPLL_NDIV_SLOWDOWN);
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if (ramp_timeout <= 0) {
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nv_error(priv, "gpcpll dynamic ramp timeout\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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static void
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_gk20a_pllg_enable(struct gk20a_clock_priv *priv)
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{
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nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE);
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nv_rd32(priv, GPCPLL_CFG);
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}
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static void
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_gk20a_pllg_disable(struct gk20a_clock_priv *priv)
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{
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nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0);
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nv_rd32(priv, GPCPLL_CFG);
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}
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static int
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_gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv, bool allow_slide)
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{
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u32 val, cfg;
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u32 m_old, pl_old, n_lo;
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/* get old coefficients */
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val = nv_rd32(priv, GPCPLL_COEFF);
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m_old = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
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pl_old = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
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/* do NDIV slide if there is no change in M and PL */
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cfg = nv_rd32(priv, GPCPLL_CFG);
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if (allow_slide && priv->m == m_old && priv->pl == pl_old &&
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(cfg & GPCPLL_CFG_ENABLE)) {
|
||||
return gk20a_pllg_slide(priv, priv->n);
|
||||
}
|
||||
|
||||
/* slide down to NDIV_LO */
|
||||
n_lo = DIV_ROUND_UP(m_old * priv->params->min_vco,
|
||||
priv->parent_rate / MHZ);
|
||||
if (allow_slide && (cfg & GPCPLL_CFG_ENABLE)) {
|
||||
int ret = gk20a_pllg_slide(priv, n_lo);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* split FO-to-bypass jump in halfs by setting out divider 1:2 */
|
||||
nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,
|
||||
0x2 << GPC2CLK_OUT_VCODIV_SHIFT);
|
||||
|
||||
/* put PLL in bypass before programming it */
|
||||
val = nv_rd32(priv, SEL_VCO);
|
||||
val &= ~(BIT(SEL_VCO_GPC2CLK_OUT_SHIFT));
|
||||
udelay(2);
|
||||
nv_wr32(priv, SEL_VCO, val);
|
||||
|
||||
/* get out from IDDQ */
|
||||
val = nv_rd32(priv, GPCPLL_CFG);
|
||||
if (val & GPCPLL_CFG_IDDQ) {
|
||||
val &= ~GPCPLL_CFG_IDDQ;
|
||||
nv_wr32(priv, GPCPLL_CFG, val);
|
||||
nv_rd32(priv, GPCPLL_CFG);
|
||||
udelay(2);
|
||||
}
|
||||
|
||||
_gk20a_pllg_disable(priv);
|
||||
|
||||
nv_debug(priv, "%s: m=%d n=%d pl=%d\n", __func__, priv->m, priv->n,
|
||||
priv->pl);
|
||||
|
||||
n_lo = DIV_ROUND_UP(priv->m * priv->params->min_vco,
|
||||
priv->parent_rate / MHZ);
|
||||
val = priv->m << GPCPLL_COEFF_M_SHIFT;
|
||||
val |= (allow_slide ? n_lo : priv->n) << GPCPLL_COEFF_N_SHIFT;
|
||||
val |= priv->pl << GPCPLL_COEFF_P_SHIFT;
|
||||
nv_wr32(priv, GPCPLL_COEFF, val);
|
||||
|
||||
_gk20a_pllg_enable(priv);
|
||||
|
||||
val = nv_rd32(priv, GPCPLL_CFG);
|
||||
if (val & GPCPLL_CFG_LOCK_DET_OFF) {
|
||||
val &= ~GPCPLL_CFG_LOCK_DET_OFF;
|
||||
nv_wr32(priv, GPCPLL_CFG, val);
|
||||
}
|
||||
|
||||
if (!nouveau_timer_wait_eq(priv, 300000, GPCPLL_CFG, GPCPLL_CFG_LOCK,
|
||||
GPCPLL_CFG_LOCK)) {
|
||||
nv_error(priv, "%s: timeout waiting for pllg lock\n", __func__);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
/* switch to VCO mode */
|
||||
nv_mask(priv, SEL_VCO, 0, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT));
|
||||
|
||||
/* restore out divider 1:1 */
|
||||
val = nv_rd32(priv, GPC2CLK_OUT);
|
||||
val &= ~GPC2CLK_OUT_VCODIV_MASK;
|
||||
udelay(2);
|
||||
nv_wr32(priv, GPC2CLK_OUT, val);
|
||||
|
||||
/* slide up to new NDIV */
|
||||
return allow_slide ? gk20a_pllg_slide(priv, priv->n) : 0;
|
||||
}
|
||||
|
||||
static int
|
||||
gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = _gk20a_pllg_program_mnp(priv, true);
|
||||
if (err)
|
||||
err = _gk20a_pllg_program_mnp(priv, false);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static void
|
||||
gk20a_pllg_disable(struct gk20a_clock_priv *priv)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* slide to VCO min */
|
||||
val = nv_rd32(priv, GPCPLL_CFG);
|
||||
if (val & GPCPLL_CFG_ENABLE) {
|
||||
u32 coeff, m, n_lo;
|
||||
|
||||
coeff = nv_rd32(priv, GPCPLL_COEFF);
|
||||
m = (coeff >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
|
||||
n_lo = DIV_ROUND_UP(m * priv->params->min_vco,
|
||||
priv->parent_rate / MHZ);
|
||||
gk20a_pllg_slide(priv, n_lo);
|
||||
}
|
||||
|
||||
/* put PLL in bypass before disabling it */
|
||||
nv_mask(priv, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0);
|
||||
|
||||
_gk20a_pllg_disable(priv);
|
||||
}
|
||||
|
||||
#define GK20A_CLK_GPC_MDIV 1000
|
||||
|
||||
static struct nouveau_clocks
|
||||
gk20a_domains[] = {
|
||||
{ nv_clk_src_crystal, 0xff },
|
||||
{ nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
|
||||
{ nv_clk_src_max }
|
||||
};
|
||||
|
||||
static struct nouveau_pstate
|
||||
gk20a_pstates[] = {
|
||||
{
|
||||
.base = {
|
||||
.domain[nv_clk_src_gpc] = 72000,
|
||||
},
|
||||
},
|
||||
{
|
||||
.base = {
|
||||
.domain[nv_clk_src_gpc] = 108000,
|
||||
},
|
||||
},
|
||||
{
|
||||
.base = {
|
||||
.domain[nv_clk_src_gpc] = 180000,
|
||||
},
|
||||
},
|
||||
{
|
||||
.base = {
|
||||
.domain[nv_clk_src_gpc] = 252000,
|
||||
},
|
||||
},
|
||||
{
|
||||
.base = {
|
||||
.domain[nv_clk_src_gpc] = 324000,
|
||||
},
|
||||
},
|
||||
{
|
||||
.base = {
|
||||
.domain[nv_clk_src_gpc] = 396000,
|
||||
},
|
||||
},
|
||||
{
|
||||
.base = {
|
||||
.domain[nv_clk_src_gpc] = 468000,
|
||||
},
|
||||
},
|
||||
{
|
||||
.base = {
|
||||
.domain[nv_clk_src_gpc] = 540000,
|
||||
},
|
||||
},
|
||||
{
|
||||
.base = {
|
||||
.domain[nv_clk_src_gpc] = 612000,
|
||||
},
|
||||
},
|
||||
{
|
||||
.base = {
|
||||
.domain[nv_clk_src_gpc] = 648000,
|
||||
},
|
||||
},
|
||||
{
|
||||
.base = {
|
||||
.domain[nv_clk_src_gpc] = 684000,
|
||||
},
|
||||
},
|
||||
{
|
||||
.base = {
|
||||
.domain[nv_clk_src_gpc] = 708000,
|
||||
},
|
||||
},
|
||||
{
|
||||
.base = {
|
||||
.domain[nv_clk_src_gpc] = 756000,
|
||||
},
|
||||
},
|
||||
{
|
||||
.base = {
|
||||
.domain[nv_clk_src_gpc] = 804000,
|
||||
},
|
||||
},
|
||||
{
|
||||
.base = {
|
||||
.domain[nv_clk_src_gpc] = 852000,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static int
|
||||
gk20a_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
|
||||
{
|
||||
struct gk20a_clock_priv *priv = (void *)clk;
|
||||
|
||||
switch (src) {
|
||||
case nv_clk_src_crystal:
|
||||
return nv_device(clk)->crystal;
|
||||
case nv_clk_src_gpc:
|
||||
gk20a_pllg_read_mnp(priv);
|
||||
return gk20a_pllg_calc_rate(priv) / GK20A_CLK_GPC_MDIV;
|
||||
default:
|
||||
nv_error(clk, "invalid clock source %d\n", src);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
gk20a_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
|
||||
{
|
||||
struct gk20a_clock_priv *priv = (void *)clk;
|
||||
|
||||
return gk20a_pllg_calc_mnp(priv, cstate->domain[nv_clk_src_gpc] *
|
||||
GK20A_CLK_GPC_MDIV);
|
||||
}
|
||||
|
||||
static int
|
||||
gk20a_clock_prog(struct nouveau_clock *clk)
|
||||
{
|
||||
struct gk20a_clock_priv *priv = (void *)clk;
|
||||
|
||||
return gk20a_pllg_program_mnp(priv);
|
||||
}
|
||||
|
||||
static void
|
||||
gk20a_clock_tidy(struct nouveau_clock *clk)
|
||||
{
|
||||
}
|
||||
|
||||
static int
|
||||
gk20a_clock_fini(struct nouveau_object *object, bool suspend)
|
||||
{
|
||||
struct gk20a_clock_priv *priv = (void *)object;
|
||||
int ret;
|
||||
|
||||
ret = nouveau_clock_fini(&priv->base, false);
|
||||
|
||||
gk20a_pllg_disable(priv);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
gk20a_clock_init(struct nouveau_object *object)
|
||||
{
|
||||
struct gk20a_clock_priv *priv = (void *)object;
|
||||
int ret;
|
||||
|
||||
nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL);
|
||||
|
||||
ret = nouveau_clock_init(&priv->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = gk20a_clock_prog(&priv->base);
|
||||
if (ret) {
|
||||
nv_error(priv, "cannot initialize clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
gk20a_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
||||
struct nouveau_oclass *oclass, void *data, u32 size,
|
||||
struct nouveau_object **pobject)
|
||||
{
|
||||
struct gk20a_clock_priv *priv;
|
||||
struct nouveau_platform_device *plat;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
/* Finish initializing the pstates */
|
||||
for (i = 0; i < ARRAY_SIZE(gk20a_pstates); i++) {
|
||||
INIT_LIST_HEAD(&gk20a_pstates[i].list);
|
||||
gk20a_pstates[i].pstate = i + 1;
|
||||
}
|
||||
|
||||
ret = nouveau_clock_create(parent, engine, oclass, gk20a_domains,
|
||||
gk20a_pstates, ARRAY_SIZE(gk20a_pstates), true, &priv);
|
||||
*pobject = nv_object(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
priv->params = &gk20a_pllg_params;
|
||||
|
||||
plat = nv_device_to_platform(nv_device(parent));
|
||||
priv->parent_rate = clk_get_rate(plat->gpu->clk);
|
||||
nv_info(priv, "parent clock rate: %d Mhz\n", priv->parent_rate / MHZ);
|
||||
|
||||
priv->base.read = gk20a_clock_read;
|
||||
priv->base.calc = gk20a_clock_calc;
|
||||
priv->base.prog = gk20a_clock_prog;
|
||||
priv->base.tidy = gk20a_clock_tidy;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct nouveau_oclass
|
||||
gk20a_clock_oclass = {
|
||||
.handle = NV_SUBDEV(CLOCK, 0xea),
|
||||
.ofuncs = &(struct nouveau_ofuncs) {
|
||||
.ctor = gk20a_clock_ctor,
|
||||
.dtor = _nouveau_subdev_dtor,
|
||||
.init = gk20a_clock_init,
|
||||
.fini = gk20a_clock_fini,
|
||||
},
|
||||
};
|
||||
Loading…
Reference in New Issue