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drm/nouveau/msvld: switch to instanced constructor 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2021-02-04 08:40:18 +10:00
parent 07a356bbe7
commit b15147bd71
16 changed files with 50 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View File

@ -60,7 +60,6 @@ struct nvkm_device {
struct notifier_block nb;
} acpi;
struct nvkm_engine *msvld;
struct nvkm_nvenc *nvenc[3];
struct nvkm_nvdec *nvdec[3];
struct nvkm_pm *pm;
@ -109,7 +108,6 @@ struct nvkm_device_chip {
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
int (*msvld )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*nvenc[3])(struct nvkm_device *, int idx, struct nvkm_nvenc **);
int (*nvdec[3])(struct nvkm_device *, int idx, struct nvkm_nvdec **);
int (*pm )(struct nvkm_device *, int idx, struct nvkm_pm **);

1
drivers/gpu/drm/nouveau/include/nvkm/core/layout.h
View File

@ -38,4 +38,5 @@ NVKM_LAYOUT_ONCE(NVKM_ENGINE_MPEG , struct nvkm_engine , mpeg)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSENC , struct nvkm_engine , msenc)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSPDEC , struct nvkm_engine , mspdec)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSPPP , struct nvkm_engine , msppp)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSVLD , struct nvkm_engine , msvld)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_VP , struct nvkm_engine , vp)

10
drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h
View File

@ -2,9 +2,9 @@
#ifndef __NVKM_MSVLD_H__
#define __NVKM_MSVLD_H__
#include <engine/falcon.h>
int g98_msvld_new(struct nvkm_device *, int, struct nvkm_engine **);
int gt215_msvld_new(struct nvkm_device *, int, struct nvkm_engine **);
int mcp89_msvld_new(struct nvkm_device *, int, struct nvkm_engine **);
int gf100_msvld_new(struct nvkm_device *, int, struct nvkm_engine **);
int gk104_msvld_new(struct nvkm_device *, int, struct nvkm_engine **);
int g98_msvld_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int gt215_msvld_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int mcp89_msvld_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int gf100_msvld_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int gk104_msvld_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
#endif

1
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
View File

@ -33,7 +33,6 @@ nvkm_subdev_type[NVKM_SUBDEV_NR] = {
#include <core/layout.h>
#undef NVKM_LAYOUT_ONCE
#undef NVKM_LAYOUT_INST
[NVKM_ENGINE_MSVLD ] = "msvld",
[NVKM_ENGINE_NVENC0 ] = "nvenc0",
[NVKM_ENGINE_NVENC1 ] = "nvenc1",
[NVKM_ENGINE_NVENC2 ] = "nvenc2",

47
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -1100,7 +1100,7 @@ nv98_chipset = {
.gr = { 0x00000001, g84_gr_new },
.mspdec = { 0x00000001, g98_mspdec_new },
.msppp = { 0x00000001, g98_msppp_new },
.msvld = g98_msvld_new,
.msvld = { 0x00000001, g98_msvld_new },
.pm = g84_pm_new,
.sec = g98_sec_new,
.sw = nv50_sw_new,
@ -1167,7 +1167,7 @@ nva3_chipset = {
.mpeg = { 0x00000001, g84_mpeg_new },
.mspdec = { 0x00000001, gt215_mspdec_new },
.msppp = { 0x00000001, gt215_msppp_new },
.msvld = gt215_msvld_new,
.msvld = { 0x00000001, gt215_msvld_new },
.pm = gt215_pm_new,
.sw = nv50_sw_new,
};
@ -1200,7 +1200,7 @@ nva5_chipset = {
.gr = { 0x00000001, gt215_gr_new },
.mspdec = { 0x00000001, gt215_mspdec_new },
.msppp = { 0x00000001, gt215_msppp_new },
.msvld = gt215_msvld_new,
.msvld = { 0x00000001, gt215_msvld_new },
.pm = gt215_pm_new,
.sw = nv50_sw_new,
};
@ -1233,7 +1233,7 @@ nva8_chipset = {
.gr = { 0x00000001, gt215_gr_new },
.mspdec = { 0x00000001, gt215_mspdec_new },
.msppp = { 0x00000001, gt215_msppp_new },
.msvld = gt215_msvld_new,
.msvld = { 0x00000001, gt215_msvld_new },
.pm = gt215_pm_new,
.sw = nv50_sw_new,
};
@ -1264,7 +1264,7 @@ nvaa_chipset = {
.gr = { 0x00000001, gt200_gr_new },
.mspdec = { 0x00000001, g98_mspdec_new },
.msppp = { 0x00000001, g98_msppp_new },
.msvld = g98_msvld_new,
.msvld = { 0x00000001, g98_msvld_new },
.pm = g84_pm_new,
.sec = g98_sec_new,
.sw = nv50_sw_new,
@ -1296,7 +1296,7 @@ nvac_chipset = {
.gr = { 0x00000001, mcp79_gr_new },
.mspdec = { 0x00000001, g98_mspdec_new },
.msppp = { 0x00000001, g98_msppp_new },
.msvld = g98_msvld_new,
.msvld = { 0x00000001, g98_msvld_new },
.pm = g84_pm_new,
.sec = g98_sec_new,
.sw = nv50_sw_new,
@ -1330,7 +1330,7 @@ nvaf_chipset = {
.gr = { 0x00000001, mcp89_gr_new },
.mspdec = { 0x00000001, gt215_mspdec_new },
.msppp = { 0x00000001, gt215_msppp_new },
.msvld = mcp89_msvld_new,
.msvld = { 0x00000001, mcp89_msvld_new },
.pm = gt215_pm_new,
.sw = nv50_sw_new,
};
@ -1366,7 +1366,7 @@ nvc0_chipset = {
.gr = { 0x00000001, gf100_gr_new },
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gf100_msvld_new,
.msvld = { 0x00000001, gf100_msvld_new },
.pm = gf100_pm_new,
.sw = gf100_sw_new,
};
@ -1402,7 +1402,7 @@ nvc1_chipset = {
.gr = { 0x00000001, gf108_gr_new },
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gf100_msvld_new,
.msvld = { 0x00000001, gf100_msvld_new },
.pm = gf108_pm_new,
.sw = gf100_sw_new,
};
@ -1438,7 +1438,7 @@ nvc3_chipset = {
.gr = { 0x00000001, gf104_gr_new },
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gf100_msvld_new,
.msvld = { 0x00000001, gf100_msvld_new },
.pm = gf100_pm_new,
.sw = gf100_sw_new,
};
@ -1474,7 +1474,7 @@ nvc4_chipset = {
.gr = { 0x00000001, gf104_gr_new },
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gf100_msvld_new,
.msvld = { 0x00000001, gf100_msvld_new },
.pm = gf100_pm_new,
.sw = gf100_sw_new,
};
@ -1510,7 +1510,7 @@ nvc8_chipset = {
.gr = { 0x00000001, gf110_gr_new },
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gf100_msvld_new,
.msvld = { 0x00000001, gf100_msvld_new },
.pm = gf100_pm_new,
.sw = gf100_sw_new,
};
@ -1546,7 +1546,7 @@ nvce_chipset = {
.gr = { 0x00000001, gf104_gr_new },
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gf100_msvld_new,
.msvld = { 0x00000001, gf100_msvld_new },
.pm = gf100_pm_new,
.sw = gf100_sw_new,
};
@ -1582,7 +1582,7 @@ nvcf_chipset = {
.gr = { 0x00000001, gf104_gr_new },
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gf100_msvld_new,
.msvld = { 0x00000001, gf100_msvld_new },
.pm = gf100_pm_new,
.sw = gf100_sw_new,
};
@ -1617,7 +1617,7 @@ nvd7_chipset = {
.gr = { 0x00000001, gf117_gr_new },
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gf100_msvld_new,
.msvld = { 0x00000001, gf100_msvld_new },
.pm = gf117_pm_new,
.sw = gf100_sw_new,
};
@ -1653,7 +1653,7 @@ nvd9_chipset = {
.gr = { 0x00000001, gf119_gr_new },
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gf100_msvld_new,
.msvld = { 0x00000001, gf100_msvld_new },
.pm = gf117_pm_new,
.sw = gf100_sw_new,
};
@ -1690,7 +1690,7 @@ nve4_chipset = {
.gr = { 0x00000001, gk104_gr_new },
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gk104_msvld_new,
.msvld = { 0x00000001, gk104_msvld_new },
.pm = gk104_pm_new,
.sw = gf100_sw_new,
};
@ -1727,7 +1727,7 @@ nve6_chipset = {
.gr = { 0x00000001, gk104_gr_new },
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gk104_msvld_new,
.msvld = { 0x00000001, gk104_msvld_new },
.pm = gk104_pm_new,
.sw = gf100_sw_new,
};
@ -1764,7 +1764,7 @@ nve7_chipset = {
.gr = { 0x00000001, gk104_gr_new },
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gk104_msvld_new,
.msvld = { 0x00000001, gk104_msvld_new },
.pm = gk104_pm_new,
.sw = gf100_sw_new,
};
@ -1826,7 +1826,7 @@ nvf0_chipset = {
.gr = { 0x00000001, gk110_gr_new },
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gk104_msvld_new,
.msvld = { 0x00000001, gk104_msvld_new },
.sw = gf100_sw_new,
};
@ -1862,7 +1862,7 @@ nvf1_chipset = {
.gr = { 0x00000001, gk110b_gr_new },
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gk104_msvld_new,
.msvld = { 0x00000001, gk104_msvld_new },
.sw = gf100_sw_new,
};
@ -1898,7 +1898,7 @@ nv106_chipset = {
.gr = { 0x00000001, gk208_gr_new },
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gk104_msvld_new,
.msvld = { 0x00000001, gk104_msvld_new },
.sw = gf100_sw_new,
};
@ -1934,7 +1934,7 @@ nv108_chipset = {
.gr = { 0x00000001, gk208_gr_new },
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gk104_msvld_new,
.msvld = { 0x00000001, gk104_msvld_new },
.sw = gf100_sw_new,
};
@ -3174,7 +3174,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
#include <core/layout.h>
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
_(NVKM_ENGINE_MSVLD , msvld);
_(NVKM_ENGINE_NVENC0 , nvenc[0]);
_(NVKM_ENGINE_NVENC1 , nvenc[1]);
_(NVKM_ENGINE_NVENC2 , nvenc[2]);

4
drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.c
View File

@ -25,7 +25,7 @@
int
nvkm_msvld_new_(const struct nvkm_falcon_func *func, struct nvkm_device *device,
int index, struct nvkm_engine **pengine)
enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine)
{
return nvkm_falcon_new_(func, device, index, true, 0x084000, pengine);
return nvkm_falcon_new_(func, device, type, inst, true, 0x084000, pengine);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c
View File

@ -43,8 +43,8 @@ g98_msvld = {
};
int
g98_msvld_new(struct nvkm_device *device, int index,
g98_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_msvld_new_(&g98_msvld, device, index, pengine);
return nvkm_msvld_new_(&g98_msvld, device, type, inst, pengine);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c
View File

@ -43,8 +43,8 @@ gf100_msvld = {
};
int
gf100_msvld_new(struct nvkm_device *device, int index,
gf100_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_msvld_new_(&gf100_msvld, device, index, pengine);
return nvkm_msvld_new_(&gf100_msvld, device, type, inst, pengine);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c
View File

@ -35,8 +35,8 @@ gk104_msvld = {
};
int
gk104_msvld_new(struct nvkm_device *device, int index,
gk104_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_msvld_new_(&gk104_msvld, device, index, pengine);
return nvkm_msvld_new_(&gk104_msvld, device, type, inst, pengine);
}

6
drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c
View File

@ -35,8 +35,8 @@ gt215_msvld = {
};
int
gt215_msvld_new(struct nvkm_device *device, int index,
struct nvkm_engine **pengine)
gt215_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_msvld_new_(&gt215_msvld, device, index, pengine);
return nvkm_msvld_new_(&gt215_msvld, device, type, inst, pengine);
}

6
drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c
View File

@ -35,8 +35,8 @@ mcp89_msvld = {
};
int
mcp89_msvld_new(struct nvkm_device *device, int index,
struct nvkm_engine **pengine)
mcp89_msvld_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_msvld_new_(&mcp89_msvld, device, index, pengine);
return nvkm_msvld_new_(&mcp89_msvld, device, type, inst, pengine);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/msvld/priv.h
View File

@ -3,8 +3,8 @@
#define __NVKM_MSVLD_PRIV_H__
#include <engine/msvld.h>
int nvkm_msvld_new_(const struct nvkm_falcon_func *, struct nvkm_device *,
int index, struct nvkm_engine **);
int nvkm_msvld_new_(const struct nvkm_falcon_func *, struct nvkm_device *, enum nvkm_subdev_type,
int, struct nvkm_engine **);
void g98_msvld_init(struct nvkm_falcon *);

4
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c
View File

@ -36,14 +36,14 @@ g98_devinit_disable(struct nvkm_devinit *init)
if (!(r001540 & 0x40000000)) {
nvkm_subdev_disable(device, NVKM_ENGINE_MSPDEC, 0);
disable |= (1ULL << NVKM_ENGINE_MSVLD);
nvkm_subdev_disable(device, NVKM_ENGINE_MSVLD, 0);
nvkm_subdev_disable(device, NVKM_ENGINE_MSPPP, 0);
}
if (!(r00154c & 0x00000004))
nvkm_subdev_disable(device, NVKM_ENGINE_DISP, 0);
if (!(r00154c & 0x00000020))
disable |= (1ULL << NVKM_ENGINE_MSVLD);
nvkm_subdev_disable(device, NVKM_ENGINE_MSVLD, 0);
if (!(r00154c & 0x00000040))
disable |= (1ULL << NVKM_ENGINE_SEC);

2
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c
View File

@ -79,7 +79,7 @@ gf100_devinit_disable(struct nvkm_devinit *init)
}
if (r022500 & 0x00000004)
disable |= (1ULL << NVKM_ENGINE_MSVLD);
nvkm_subdev_disable(device, NVKM_ENGINE_MSVLD, 0);
if (r022500 & 0x00000008)
nvkm_subdev_disable(device, NVKM_ENGINE_MSENC, 0);
if (r022500 & 0x00000100)

2
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c
View File

@ -78,7 +78,7 @@ gt215_devinit_disable(struct nvkm_devinit *init)
if (!(r00154c & 0x00000004))
nvkm_subdev_disable(device, NVKM_ENGINE_DISP, 0);
if (!(r00154c & 0x00000020))
disable |= (1ULL << NVKM_ENGINE_MSVLD);
nvkm_subdev_disable(device, NVKM_ENGINE_MSVLD, 0);
if (!(r00154c & 0x00000200))
nvkm_subdev_disable(device, NVKM_ENGINE_CE, 0);

2
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c
View File

@ -42,7 +42,7 @@ mcp89_devinit_disable(struct nvkm_devinit *init)
if (!(r00154c & 0x00000004))
nvkm_subdev_disable(device, NVKM_ENGINE_DISP, 0);
if (!(r00154c & 0x00000020))
disable |= (1ULL << NVKM_ENGINE_MSVLD);
nvkm_subdev_disable(device, NVKM_ENGINE_MSVLD, 0);
if (!(r00154c & 0x00000040))
disable |= (1ULL << NVKM_ENGINE_VIC);
if (!(r00154c & 0x00000200))