mirror of https://gitee.com/openkylin/linux.git
hwrng: omap - Fix clock resource by adding a register clock
On Armada 7K/8K we need to explicitly enable the register clock. This clock is optional because not all the SoCs using this IP need it but at least for Armada 7K/8K it is actually mandatory. The binding documentation is updating accordingly. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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@ -13,7 +13,12 @@ Required properties:
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- interrupts : the interrupt number for the RNG module.
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Used for "ti,omap4-rng" and "inside-secure,safexcel-eip76"
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- clocks: the trng clock source. Only mandatory for the
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"inside-secure,safexcel-eip76" compatible.
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"inside-secure,safexcel-eip76" compatible, the second clock is
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needed for the Armada 7K/8K SoCs
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- clock-names: mandatory if there is a second clock, in this case the
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name must be "core" for the first clock and "reg" for the second
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one
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Example:
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/* AM335x */
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@ -150,6 +150,7 @@ struct omap_rng_dev {
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const struct omap_rng_pdata *pdata;
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struct hwrng rng;
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struct clk *clk;
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struct clk *clk_reg;
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};
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static inline u32 omap_rng_read(struct omap_rng_dev *priv, u16 reg)
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@ -480,6 +481,19 @@ static int omap_rng_probe(struct platform_device *pdev)
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}
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}
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priv->clk_reg = devm_clk_get(&pdev->dev, "reg");
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if (IS_ERR(priv->clk_reg) && PTR_ERR(priv->clk_reg) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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if (!IS_ERR(priv->clk_reg)) {
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ret = clk_prepare_enable(priv->clk_reg);
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if (ret) {
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dev_err(&pdev->dev,
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"Unable to enable the register clk: %d\n",
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ret);
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goto err_register;
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}
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}
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ret = (dev->of_node) ? of_get_omap_rng_device_details(priv, pdev) :
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get_omap_rng_device_details(priv);
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if (ret)
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@ -499,6 +513,7 @@ static int omap_rng_probe(struct platform_device *pdev)
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pm_runtime_put_sync(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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clk_disable_unprepare(priv->clk_reg);
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clk_disable_unprepare(priv->clk);
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err_ioremap:
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dev_err(dev, "initialization failed.\n");
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@ -517,6 +532,7 @@ static int omap_rng_remove(struct platform_device *pdev)
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pm_runtime_disable(&pdev->dev);
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clk_disable_unprepare(priv->clk);
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clk_disable_unprepare(priv->clk_reg);
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return 0;
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}
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