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drm/amdgpu: update the calc algorithm of umc ecc error count 

the initial value of ecc error count can be adjusted

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tao Zhou 2019-07-29 17:19:57 +08:00 committed by Alex Deucher
parent b7f92097f5
commit b1a5895352
1 changed files with 6 additions and 4 deletions
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10
drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
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@ -98,9 +98,10 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel); WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset); ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset);
*error_count += *error_count +=
REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt); (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
UMC_V6_1_CE_CNT_INIT);
/* clear the lower chip err count */ /* clear the lower chip err count */
WREG32(ecc_err_cnt_addr + umc_reg_offset, 0); WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
/* select the higher chip and check the err counter */ /* select the higher chip and check the err counter */
ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel, ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
@ -108,9 +109,10 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel); WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset); ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset);
*error_count += *error_count +=
REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt); (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
UMC_V6_1_CE_CNT_INIT);
/* clear the higher chip err count */ /* clear the higher chip err count */
WREG32(ecc_err_cnt_addr + umc_reg_offset, 0); WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
/* check for SRAM correctable error /* check for SRAM correctable error
MCUMC_STATUS is a 64 bit register */ MCUMC_STATUS is a 64 bit register */