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drm/amdgpu: adjust HDP write queue flushing for tlb invalidation 

Separate tlb invalidation and hdp flushing and move the HDP
flush to the caller.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2018-01-05 10:25:57 -05:00
parent 73c732405f
commit b1d128689f
6 changed files with 4 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
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@ -247,6 +247,7 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
} }
} }
mb(); mb();
amdgpu_asic_flush_hdp(adev);
amdgpu_gart_flush_gpu_tlb(adev, 0); amdgpu_gart_flush_gpu_tlb(adev, 0);
return 0; return 0;
} }
@ -329,6 +330,7 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
return r; return r;
mb(); mb();
amdgpu_asic_flush_hdp(adev);
amdgpu_gart_flush_gpu_tlb(adev, 0); amdgpu_gart_flush_gpu_tlb(adev, 0);
return 0; return 0;
} }

2
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
View File

@ -856,6 +856,7 @@ int amdgpu_vm_update_directories(struct amdgpu_device *adev,
if (vm->use_cpu_for_update) { if (vm->use_cpu_for_update) {
/* Flush HDP */ /* Flush HDP */
mb(); mb();
amdgpu_asic_flush_hdp(adev);
amdgpu_gart_flush_gpu_tlb(adev, 0); amdgpu_gart_flush_gpu_tlb(adev, 0);
} else if (params.ib->length_dw == 0) { } else if (params.ib->length_dw == 0) {
amdgpu_job_free(job); amdgpu_job_free(job);
@ -1457,6 +1458,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
if (vm->use_cpu_for_update) { if (vm->use_cpu_for_update) {
/* Flush HDP */ /* Flush HDP */
mb(); mb();
amdgpu_asic_flush_hdp(adev);
amdgpu_gart_flush_gpu_tlb(adev, 0); amdgpu_gart_flush_gpu_tlb(adev, 0);
} }

2
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
View File

@ -360,8 +360,6 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
uint32_t vmid) uint32_t vmid)
{ {
WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
} }

3
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
View File

@ -432,9 +432,6 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
uint32_t vmid) uint32_t vmid)
{ {
/* flush hdp cache */
WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
/* bits 0-15 are the VM contexts0-15 */ /* bits 0-15 are the VM contexts0-15 */
WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
} }

3
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
View File

@ -607,9 +607,6 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
uint32_t vmid) uint32_t vmid)
{ {
/* flush hdp cache */
WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
/* bits 0-15 are the VM contexts0-15 */ /* bits 0-15 are the VM contexts0-15 */
WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
} }

3
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
View File

@ -330,9 +330,6 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
const unsigned eng = 17; const unsigned eng = 17;
unsigned i, j; unsigned i, j;
/* flush hdp cache */
adev->nbio_funcs->hdp_flush(adev);
spin_lock(&adev->mc.invalidate_lock); spin_lock(&adev->mc.invalidate_lock);
for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {