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ARC: [plat-eznps] Use dedicated SMP barriers 

NPS device got 256 cores and each got 16 HW threads (SMT).
We use EZchip dedicated ISA to trigger HW scheduler of the
core that current HW thread belongs to.
This scheduling makes sure that data beyond barrier is available
to all HW threads in core and by that to all in device (4K).

Signed-off-by: Noam Camus <noamc@ezchip.com>
Cc: Peter Zijlstra <peterz@infradead.org>
This commit is contained in:
Noam Camus 2015-04-10 21:28:50 +03:00 committed by Vineet Gupta
parent a5a10d99a9
commit b1f2f6f3cf
1 changed files with 9 additions and 3 deletions
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12
arch/arc/include/asm/barrier.h
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@ -30,9 +30,7 @@
#define rmb() asm volatile("dmb 1\n" : : : "memory")
#define wmb() asm volatile("dmb 2\n" : : : "memory")
#endif
#ifdef CONFIG_ISA_ARCOMPACT
#elif !defined(CONFIG_ARC_PLAT_EZNPS) /* CONFIG_ISA_ARCOMPACT */
/*
* ARCompact based cores (ARC700) only have SYNC instruction which is super
@ -41,6 +39,14 @@
*/
#define mb() asm volatile("sync\n" : : : "memory")
#else /* CONFIG_ARC_PLAT_EZNPS */
#include <plat/ctop.h>
#define mb() asm volatile (".word %0" : : "i"(CTOP_INST_SCHD_RW) : "memory")
#define rmb() asm volatile (".word %0" : : "i"(CTOP_INST_SCHD_RD) : "memory")
#endif
#include <asm-generic/barrier.h>