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Amlogic clock headers and DT binding updates for v4.12
- add clocks for I2S and Mali -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJY5CdGAAoJEFk3GJrT+8ZlCNIP/2LrvbcOfubJZ36K2Twbx1QL u0xx7TjVJyMREBzN0FmINs6O1h0Q29xahGj5GfOXY4/SY4TYfibkg8K3Tn7vsDYG 7YAe/bMC2Ju+cx2NIMEuC+T+Fu05dDvTWXBwfnfMnWua+toLZ0Ej2cdvo8mx0xuE dIhiwb/6cB7TcJRHzmEqWN2pHxtqxwdGUPPxhiD0W6jw+I6Oo8Ampgdyk9KCWWwd mGvcrTY9Z9R5iKRFzcfZJ71aPgEDsnIFhV+nqOHjxJoWauPZmysth6fM6WNn7oJH Oy5hqFZjE27KkBkl55Mve7xuU/QiJJhuMc3lc4o47Vq5b8pNxU9G6DUI7s/hIVXo 4TFG7bEsB17UK7d8GWOcFnsPbe4n738VOWPbX7WcoYH0RzcPVs+5nSx8eVq46yc4 h/U+PIyE5psUwULWDHYZY37eGhxuDJ3cxQ3X+TocwzpMG00Wp4H1YXRZzBRwIaSg b+DjUwFgwL0ZPOeM5pf+e56Y7eV9+BNC5VpDfxpEiC3UwAj09fEhCAVcDNLxcRHV neuAe5nequhMxjxp3FcReS9EgTJDur+MT0+i4jpRlGONOJ9zeVzLe/P6i1zZocN2 fqSoC3zOHZcTwrUWQXRwmoLlBoClle+gIcnZnbF81PZZmiGNxtWLzD2uu4i4WbZk tJgI7qEo6GcNxRB+wKD8 =rf2z -----END PGP SIGNATURE----- Merge tag 'amlogic-clk-headers' into v4.12/dt64 Amlogic clock headers and DT binding updates for v4.12 - add clocks for I2S and Mali # gpg: Signature made Tue Apr 4 16:07:50 2017 PDT using RSA key ID D3FBC665 # gpg: Good signature from "Kevin Hilman <khilman@kernel.org>" [ultimate] # gpg: aka "Kevin Hilman <khilman@deeprootsystems.com>" [ultimate] # gpg: aka "Kevin Hilman <khilman@gmail.com>" [ultimate] # gpg: aka "Kevin Hilman <khilman@baylibre.com>" [ultimate] * tag 'amlogic-clk-headers': dt-bindings: clock: gxbb-clkc: Add GXL compatible variant clk: meson-gxbb: Expose GP0 dt-bindings clock id clk: meson-gxbb: Add MALI clock IDS dt-bindings: clk: gxbb: expose i2s output clock gates
This commit is contained in:
Kevin Hilman
commit
b212117014
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@ -5,7 +5,8 @@ controllers within the SoC.
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Required Properties:
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- compatible: should be "amlogic,gxbb-clkc"
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- compatible: should be "amlogic,gxbb-clkc" for GXBB SoC,
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or "amlogic,gxl-clkc" for GXL and GXM SoC.
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- reg: physical base address of the clock controller and length of memory
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mapped region.
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@ -177,7 +177,7 @@
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/* CLKID_FCLK_DIV4 */
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#define CLKID_FCLK_DIV5 7
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#define CLKID_FCLK_DIV7 8
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#define CLKID_GP0_PLL 9
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/* CLKID_GP0_PLL */
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#define CLKID_MPEG_SEL 10
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#define CLKID_MPEG_DIV 11
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/* CLKID_CLK81 */
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@ -206,16 +206,16 @@
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#define CLKID_I2S_SPDIF 35
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/* CLKID_ETH */
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#define CLKID_DEMUX 37
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#define CLKID_AIU_GLUE 38
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/* CLKID_AIU_GLUE */
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#define CLKID_IEC958 39
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#define CLKID_I2S_OUT 40
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/* CLKID_I2S_OUT */
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#define CLKID_AMCLK 41
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#define CLKID_AIFIFO2 42
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#define CLKID_MIXER 43
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#define CLKID_MIXER_IFACE 44
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/* CLKID_MIXER_IFACE */
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#define CLKID_ADC 45
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#define CLKID_BLKMV 46
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#define CLKID_AIU 47
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/* CLKID_AIU */
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#define CLKID_UART1 48
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#define CLKID_G2D 49
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/* CLKID_USB0 */
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@ -248,7 +248,7 @@
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/* CLKID_GCLK_VENCI_INT0 */
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#define CLKID_GCLK_VENCI_INT 78
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#define CLKID_DAC_CLK 79
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#define CLKID_AOCLK_GATE 80
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/* CLKID_AOCLK_GATE */
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#define CLKID_IEC958_GATE 81
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#define CLKID_ENC480P 82
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#define CLKID_RNG1 83
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@ -268,8 +268,15 @@
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/* CLKID_SAR_ADC_CLK */
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/* CLKID_SAR_ADC_SEL */
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#define CLKID_SAR_ADC_DIV 99
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/* CLKID_MALI_0_SEL */
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#define CLKID_MALI_0_DIV 101
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/* CLKID_MALI_0 */
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/* CLKID_MALI_1_SEL */
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#define CLKID_MALI_1_DIV 104
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/* CLKID_MALI_1 */
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/* CLKID_MALI */
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#define NR_CLKS 100
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#define NR_CLKS 107
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/* include the CLKIDs that have been made part of the stable DT binding */
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#include <dt-bindings/clock/gxbb-clkc.h>
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@ -10,12 +10,17 @@
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#define CLKID_FCLK_DIV2 4
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#define CLKID_FCLK_DIV3 5
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#define CLKID_FCLK_DIV4 6
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#define CLKID_GP0_PLL 9
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#define CLKID_CLK81 12
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#define CLKID_MPLL2 15
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#define CLKID_SPI 34
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#define CLKID_I2C 22
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#define CLKID_SAR_ADC 23
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#define CLKID_ETH 36
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#define CLKID_AIU_GLUE 38
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#define CLKID_I2S_OUT 40
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#define CLKID_MIXER_IFACE 44
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#define CLKID_AIU 47
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#define CLKID_USB0 50
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#define CLKID_USB1 51
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#define CLKID_USB 55
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@ -24,11 +29,17 @@
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#define CLKID_USB0_DDR_BRIDGE 65
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#define CLKID_SANA 69
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#define CLKID_GCLK_VENCI_INT0 77
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#define CLKID_AOCLK_GATE 80
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#define CLKID_AO_I2C 93
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#define CLKID_SD_EMMC_A 94
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#define CLKID_SD_EMMC_B 95
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#define CLKID_SD_EMMC_C 96
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#define CLKID_SAR_ADC_CLK 97
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#define CLKID_SAR_ADC_SEL 98
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#define CLKID_MALI_0_SEL 100
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#define CLKID_MALI_0 102
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#define CLKID_MALI_1_SEL 103
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#define CLKID_MALI_1 105
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#define CLKID_MALI 106
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#endif /* __GXBB_CLKC_H */
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