mirror of https://gitee.com/openkylin/linux.git
x86, cpa: make the kernel physical mapping initialization a two pass sequence, fix
Jeremy Fitzhardinge wrote: > I'd noticed that current tip/master hasn't been booting under Xen, and I > just got around to bisecting it down to this change. > > commit 065ae73c5462d42e9761afb76f2b52965ff45bd6 > Author: Suresh Siddha <suresh.b.siddha@intel.com> > > x86, cpa: make the kernel physical mapping initialization a two pass sequence > > This patch is causing Xen to fail various pagetable updates because it > ends up remapping pagetables to RW, which Xen explicitly prohibits (as > that would allow guests to make arbitrary changes to pagetables, rather > than have them mediated by the hypervisor). Instead of making init a two pass sequence, to satisfy the Intel's TLB Application note (developer.intel.com/design/processor/applnots/317080.pdf Section 6 page 26), we preserve the original page permissions when fragmenting the large mappings and don't touch the existing memory mapping (which satisfies Xen's requirements). Only open issue is: on a native linux kernel, we will go back to mapping the first 0-1GB kernel identity mapping as executable (because of the static mapping setup in head_64.S). We can fix this in a different patch if needed. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Acked-by: Jeremy Fitzhardinge <jeremy@goop.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Suresh Siddha
Ingo Molnar
parent
ad2cde16a2
commit
b27a43c1e9
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@ -270,10 +270,9 @@ static __ref void unmap_low_page(void *adr)
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early_iounmap(adr, PAGE_SIZE);
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}
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static int physical_mapping_iter;
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static unsigned long __meminit
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phys_pte_init(pte_t *pte_page, unsigned long addr, unsigned long end)
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phys_pte_init(pte_t *pte_page, unsigned long addr, unsigned long end,
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pgprot_t prot)
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{
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unsigned pages = 0;
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unsigned long last_map_addr = end;
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@ -291,35 +290,40 @@ phys_pte_init(pte_t *pte_page, unsigned long addr, unsigned long end)
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break;
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}
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/*
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* We will re-use the existing mapping.
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* Xen for example has some special requirements, like mapping
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* pagetable pages as RO. So assume someone who pre-setup
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* these mappings are more intelligent.
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*/
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if (pte_val(*pte))
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goto repeat_set_pte;
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continue;
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if (0)
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printk(" pte=%p addr=%lx pte=%016lx\n",
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pte, addr, pfn_pte(addr >> PAGE_SHIFT, PAGE_KERNEL).pte);
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pages++;
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repeat_set_pte:
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set_pte(pte, pfn_pte(addr >> PAGE_SHIFT, PAGE_KERNEL));
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set_pte(pte, pfn_pte(addr >> PAGE_SHIFT, prot));
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last_map_addr = (addr & PAGE_MASK) + PAGE_SIZE;
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}
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if (physical_mapping_iter == 1)
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update_page_count(PG_LEVEL_4K, pages);
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return last_map_addr;
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}
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static unsigned long __meminit
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phys_pte_update(pmd_t *pmd, unsigned long address, unsigned long end)
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phys_pte_update(pmd_t *pmd, unsigned long address, unsigned long end,
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pgprot_t prot)
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{
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pte_t *pte = (pte_t *)pmd_page_vaddr(*pmd);
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return phys_pte_init(pte, address, end);
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return phys_pte_init(pte, address, end, prot);
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}
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static unsigned long __meminit
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phys_pmd_init(pmd_t *pmd_page, unsigned long address, unsigned long end,
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unsigned long page_size_mask)
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unsigned long page_size_mask, pgprot_t prot)
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{
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unsigned long pages = 0;
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unsigned long last_map_addr = end;
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@ -330,6 +334,7 @@ phys_pmd_init(pmd_t *pmd_page, unsigned long address, unsigned long end,
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unsigned long pte_phys;
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pmd_t *pmd = pmd_page + pmd_index(address);
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pte_t *pte;
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pgprot_t new_prot = prot;
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if (address >= end) {
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if (!after_bootmem) {
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@ -343,45 +348,58 @@ phys_pmd_init(pmd_t *pmd_page, unsigned long address, unsigned long end,
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if (!pmd_large(*pmd)) {
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spin_lock(&init_mm.page_table_lock);
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last_map_addr = phys_pte_update(pmd, address,
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end);
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end, prot);
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spin_unlock(&init_mm.page_table_lock);
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continue;
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}
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goto repeat_set_pte;
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/*
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* If we are ok with PG_LEVEL_2M mapping, then we will
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* use the existing mapping,
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*
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* Otherwise, we will split the large page mapping but
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* use the same existing protection bits except for
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* large page, so that we don't violate Intel's TLB
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* Application note (317080) which says, while changing
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* the page sizes, new and old translations should
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* not differ with respect to page frame and
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* attributes.
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*/
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if (page_size_mask & (1 << PG_LEVEL_2M))
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continue;
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new_prot = pte_pgprot(pte_clrhuge(*(pte_t *)pmd));
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}
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if (page_size_mask & (1<<PG_LEVEL_2M)) {
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pages++;
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repeat_set_pte:
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spin_lock(&init_mm.page_table_lock);
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set_pte((pte_t *)pmd,
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pfn_pte(address >> PAGE_SHIFT, PAGE_KERNEL_LARGE));
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pfn_pte(address >> PAGE_SHIFT,
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__pgprot(pgprot_val(prot) | _PAGE_PSE)));
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spin_unlock(&init_mm.page_table_lock);
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last_map_addr = (address & PMD_MASK) + PMD_SIZE;
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continue;
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}
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pte = alloc_low_page(&pte_phys);
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last_map_addr = phys_pte_init(pte, address, end);
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last_map_addr = phys_pte_init(pte, address, end, new_prot);
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unmap_low_page(pte);
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spin_lock(&init_mm.page_table_lock);
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pmd_populate_kernel(&init_mm, pmd, __va(pte_phys));
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spin_unlock(&init_mm.page_table_lock);
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}
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if (physical_mapping_iter == 1)
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update_page_count(PG_LEVEL_2M, pages);
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return last_map_addr;
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}
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static unsigned long __meminit
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phys_pmd_update(pud_t *pud, unsigned long address, unsigned long end,
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unsigned long page_size_mask)
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unsigned long page_size_mask, pgprot_t prot)
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{
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pmd_t *pmd = pmd_offset(pud, 0);
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unsigned long last_map_addr;
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last_map_addr = phys_pmd_init(pmd, address, end, page_size_mask);
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last_map_addr = phys_pmd_init(pmd, address, end, page_size_mask, prot);
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__flush_tlb_all();
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return last_map_addr;
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}
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@ -398,6 +416,7 @@ phys_pud_init(pud_t *pud_page, unsigned long addr, unsigned long end,
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unsigned long pmd_phys;
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pud_t *pud = pud_page + pud_index(addr);
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pmd_t *pmd;
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pgprot_t prot = PAGE_KERNEL;
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if (addr >= end)
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break;
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@ -411,16 +430,28 @@ phys_pud_init(pud_t *pud_page, unsigned long addr, unsigned long end,
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if (pud_val(*pud)) {
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if (!pud_large(*pud)) {
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last_map_addr = phys_pmd_update(pud, addr, end,
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page_size_mask);
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page_size_mask, prot);
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continue;
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}
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goto repeat_set_pte;
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/*
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* If we are ok with PG_LEVEL_1G mapping, then we will
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* use the existing mapping.
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*
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* Otherwise, we will split the gbpage mapping but use
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* the same existing protection bits except for large
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* page, so that we don't violate Intel's TLB
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* Application note (317080) which says, while changing
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* the page sizes, new and old translations should
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* not differ with respect to page frame and
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* attributes.
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*/
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if (page_size_mask & (1 << PG_LEVEL_1G))
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continue;
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prot = pte_pgprot(pte_clrhuge(*(pte_t *)pud));
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}
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if (page_size_mask & (1<<PG_LEVEL_1G)) {
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pages++;
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repeat_set_pte:
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spin_lock(&init_mm.page_table_lock);
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set_pte((pte_t *)pud,
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pfn_pte(addr >> PAGE_SHIFT, PAGE_KERNEL_LARGE));
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@ -430,7 +461,8 @@ phys_pud_init(pud_t *pud_page, unsigned long addr, unsigned long end,
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}
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pmd = alloc_low_page(&pmd_phys);
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last_map_addr = phys_pmd_init(pmd, addr, end, page_size_mask);
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last_map_addr = phys_pmd_init(pmd, addr, end, page_size_mask,
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prot);
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unmap_low_page(pmd);
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spin_lock(&init_mm.page_table_lock);
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@ -439,7 +471,6 @@ phys_pud_init(pud_t *pud_page, unsigned long addr, unsigned long end,
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}
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__flush_tlb_all();
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if (physical_mapping_iter == 1)
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update_page_count(PG_LEVEL_1G, pages);
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return last_map_addr;
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@ -505,54 +536,15 @@ static void __init init_gbpages(void)
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direct_gbpages = 0;
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}
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static int is_kernel(unsigned long pfn)
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{
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unsigned long pg_addresss = pfn << PAGE_SHIFT;
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if (pg_addresss >= (unsigned long) __pa(_text) &&
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pg_addresss < (unsigned long) __pa(_end))
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return 1;
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return 0;
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}
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static unsigned long __init kernel_physical_mapping_init(unsigned long start,
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unsigned long end,
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unsigned long page_size_mask)
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{
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unsigned long next, last_map_addr;
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u64 cached_supported_pte_mask = __supported_pte_mask;
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unsigned long cache_start = start;
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unsigned long cache_end = end;
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unsigned long next, last_map_addr = end;
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/*
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* First iteration will setup identity mapping using large/small pages
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* based on page_size_mask, with other attributes same as set by
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* the early code in head_64.S
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*
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* Second iteration will setup the appropriate attributes
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* as desired for the kernel identity mapping.
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*
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* This two pass mechanism conforms to the TLB app note which says:
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*
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* "Software should not write to a paging-structure entry in a way
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* that would change, for any linear address, both the page size
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* and either the page frame or attributes."
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*
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* For now, only difference between very early PTE attributes used in
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* head_64.S and here is _PAGE_NX.
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*/
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BUILD_BUG_ON((__PAGE_KERNEL_LARGE & ~__PAGE_KERNEL_IDENT_LARGE_EXEC)
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!= _PAGE_NX);
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__supported_pte_mask &= ~(_PAGE_NX);
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physical_mapping_iter = 1;
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repeat:
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last_map_addr = cache_end;
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start = (unsigned long)__va(cache_start);
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end = (unsigned long)__va(cache_end);
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start = (unsigned long)__va(start);
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end = (unsigned long)__va(end);
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for (; start < end; start = next) {
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pgd_t *pgd = pgd_offset_k(start);
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@ -564,21 +556,11 @@ static unsigned long __init kernel_physical_mapping_init(unsigned long start,
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next = end;
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if (pgd_val(*pgd)) {
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/*
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* Static identity mappings will be overwritten
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* with run-time mappings. For example, this allows
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* the static 0-1GB identity mapping to be mapped
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* non-executable with this.
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*/
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if (is_kernel(pte_pfn(*((pte_t *) pgd))))
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goto realloc;
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last_map_addr = phys_pud_update(pgd, __pa(start),
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__pa(end), page_size_mask);
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continue;
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}
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realloc:
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pud = alloc_low_page(&pud_phys);
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last_map_addr = phys_pud_init(pud, __pa(start), __pa(next),
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page_size_mask);
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@ -590,15 +572,6 @@ static unsigned long __init kernel_physical_mapping_init(unsigned long start,
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}
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__flush_tlb_all();
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if (physical_mapping_iter == 1) {
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physical_mapping_iter = 2;
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/*
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* Second iteration will set the actual desired PTE attributes.
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*/
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__supported_pte_mask = cached_supported_pte_mask;
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goto repeat;
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}
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return last_map_addr;
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}
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