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mvebu dt64 for 4.15 (part 1) 

On Armada 7K/8k:
 - Improve network support at SoC and board level
 - Enable watchdog
 - Add UART muxing
 - On 7040 DB: add CD SDIO and NAND support
 - On 8040 DB: add PCIE more ports and SPI1
 
 On Armada 37xx:
  - Fix UART register size
  - Add vmmc regulator for SD on 3720 DB
 -----BEGIN PGP SIGNATURE-----
 
 iIEEABECAEEWIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWeoPnCMcZ3JlZ29yeS5j
 bGVtZW50QGZyZWUtZWxlY3Ryb25zLmNvbQAKCRALBhiOFHI71eWeAJ4yqhFToGh9
 bLvyANmN33Lp0kYfEwCeKTJv715mvxAfJMYUMX7CUmgEAOs=
 =9sls
 -----END PGP SIGNATURE-----

Merge tag 'mvebu-dt64-4.15-1' of git://git.infradead.org/linux-mvebu into next/dt

Pull "mvebu dt64 for 4.15 (part 1)" from Gregory CLEMENT:

On Armada 7K/8k:
- Improve network support at SoC and board level
- Enable watchdog
- Add UART muxing
- On 7040 DB: add CD SDIO and NAND support
- On 8040 DB: add PCIE more ports and SPI1

On Armada 37xx:
 - Fix UART register size
 - Add vmmc regulator for SD on 3720 DB

* tag 'mvebu-dt64-4.15-1' of git://git.infradead.org/linux-mvebu:
  arm64: dts: marvell: 7040-db: Add the carrier detect pin for SD card on CP
  arm64: dts: marvell: 7040-db: Document the gpio expander
  arm64: dts: marvell: enable additional PCIe ports on Armada 8040 DB
  arm64: dts: marvell: add NAND support on the 7040-DB board
  arm64: dts: marvell: Enable Armada-8040-DB CPS SPI1
  arm64: dts: marvell: 8040-db: enable the SFP ports
  arm64: dts: marvell: 7040-db: enable the SFP port
  arm64: dts: marvell: 7040-db: add comphy reference to Ethernet port
  arm64: dts: marvell: mcbin: add comphy references to Ethernet ports
  arm64: dts: marvell: 37xx: remove empty line
  arm64: dts: marvell: cp110: add PPv2 port interrupts
  arm64: dts: marvell: add comphy nodes on cp110 master and slave
  arm64: dts: marvell: extend the cp110 syscon register area length
  arm64: dts: marvell: enable AP806 watchdog
  arm64: dts: marvell: Fix A37xx UART0 register size
  arm64: dts: marvell: armada-3720-db: Add vmmc regulator for SD slot
  arm64: dts: marvell: add UART muxing on Armada 7K/8K
This commit is contained in:
Arnd Bergmann 2017-10-30 14:32:45 +01:00
parent a2c614a7db c4e3bf290c
commit b295477e00
10 changed files with 261 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/serial/mvebu-uart.txt
View File

@ -8,6 +8,6 @@ Required properties:
Example:
serial@12000 {
compatible = "marvell,armada-3700-uart";
reg = <0x12000 0x400>;
reg = <0x12000 0x200>;
interrupts = <43>;
};

11
arch/arm64/boot/dts/marvell/armada-3720-db.dts
View File

@ -94,6 +94,16 @@ vcc_sd_reg1: regulator {
3300000 0x0>;
enable-active-high;
};
vcc_sd_reg2: regulator-vmcc {
compatible = "regulator-fixed";
regulator-name = "vcc_sd2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
gpio = <&gpio_exp 4 GPIO_ACTIVE_HIGH>;
};
};
/* Gigabit module on CON19(V2.0)/CON21(V1.4) */
@ -179,6 +189,7 @@ &sdhci1 {
bus-width = <4>;
marvell,pad-type = "sd";
vqmmc-supply = <&vcc_sd_reg1>;
vmmc-supply = <&vcc_sd_reg2>;
status = "okay";
};

3
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
View File

@ -134,7 +134,7 @@ i2c1: i2c@11080 {
uart0: serial@12000 {
compatible = "marvell,armada-3700-uart";
reg = <0x12000 0x400>;
reg = <0x12000 0x200>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -183,7 +183,6 @@ gpionb: gpio {
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
};
xtalclk: xtal-clk {

55
arch/arm64/boot/dts/marvell/armada-7040-db.dts
View File

@ -124,6 +124,8 @@ partition@400000 {
&uart0 {
status = "okay";
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
};
@ -141,9 +143,49 @@ expander0: pca9555@21 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x21>;
/*
* IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect
* IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit
* IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN
* IO0_3: USB2_DEVICE_DETECT
* IO0_4: GPIO_0 IO1_4: SD_Status
* IO0_5: GPIO_1 IO1_5: LDO_5V_Enable
* IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC
* IO0_7: IO1_7: SDIO_Vcntrl
*/
};
};
&cpm_nand {
/*
* SPI on CPM and NAND have common pins on this board. We can
* use only one at a time. To enable the NAND (whihch will
* disable the SPI), the "status = "okay";" line have to be
* added here.
*/
num-cs = <1>;
pinctrl-0 = <&nand_pins>, <&nand_rb>;
pinctrl-names = "default";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
partition@0 {
label = "U-Boot";
reg = <0 0x200000>;
};
partition@200000 {
label = "Linux";
reg = <0x200000 0xe00000>;
};
partition@1000000 {
label = "Filesystem";
reg = <0x1000000 0x3f000000>;
};
};
&cpm_spi1 {
status = "okay";
@ -197,7 +239,7 @@ &cpm_sdhci0 {
status = "okay";
bus-width = <4>;
no-1-8-v;
non-removable;
cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
};
&cpm_mdio {
@ -215,10 +257,21 @@ &cpm_ethernet {
status = "okay";
};
&cpm_eth0 {
status = "okay";
/* Network PHY */
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cpm_comphy2 0>;
};
&cpm_eth1 {
status = "okay";
/* Network PHY */
phy = <&phy0>;
phy-mode = "sgmii";
/* Generic PHY, providing serdes lanes */
phys = <&cpm_comphy0 1>;
};
&cpm_eth2 {

14
arch/arm64/boot/dts/marvell/armada-70x0.dtsi
View File

@ -64,5 +64,19 @@ &cpm_gpio2 {
&cpm_syscon0 {
cpm_pinctrl: pinctrl {
compatible = "marvell,armada-7k-pinctrl";
nand_pins: nand-pins {
marvell,pins =
"mpp15", "mpp16", "mpp17", "mpp18",
"mpp19", "mpp20", "mpp21", "mpp22",
"mpp23", "mpp24", "mpp25", "mpp26",
"mpp27";
marvell,function = "dev";
};
nand_rb: nand-rb {
marvell,pins = "mpp13";
marvell,function = "nf";
};
};
};

57
arch/arm64/boot/dts/marvell/armada-8040-db.dts
View File

@ -139,8 +139,14 @@ partition@400000 {
/* Accessible over the mini-USB CON9 connector on the main board */
&uart0 {
status = "okay";
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
};
/* CON6 on CP0 expansion */
&cpm_pcie0 {
status = "okay";
};
/* CON5 on CP0 expansion */
&cpm_pcie2 {
@ -200,12 +206,27 @@ &cpm_ethernet {
status = "okay";
};
&cpm_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
};
&cpm_eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
/* CON6 on CP1 expansion */
&cps_pcie0 {
status = "okay";
};
/* CON7 on CP1 expansion */
&cps_pcie1 {
status = "okay";
};
/* CON5 on CP1 expansion */
&cps_pcie2 {
status = "okay";
@ -216,6 +237,37 @@ &cps_i2c0 {
clock-frequency = <100000>;
};
&cps_spi1 {
status = "okay";
spi-flash@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <20000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Boot";
reg = <0x0 0x200000>;
};
partition@200000 {
label = "Filesystem";
reg = <0x200000 0xd00000>;
};
partition@f00000 {
label = "Boot_2nd";
reg = <0xf00000 0x100000>;
};
};
};
};
/* CON4 on CP1 expansion */
&cps_sata0 {
status = "okay";
@ -244,6 +296,11 @@ &cps_ethernet {
status = "okay";
};
&cps_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
};
&cps_eth1 {
status = "okay";
phy = <&phy0>;

11
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
View File

@ -101,6 +101,8 @@ usb3h0_phy: usb3_phy0 {
&uart0 {
status = "okay";
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
};
&ap_sdhci0 {
@ -222,8 +224,11 @@ &cpm_ethernet {
&cpm_eth0 {
status = "okay";
/* Network PHY */
phy = <&phy0>;
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cpm_comphy4 0>;
};
&cpm_sata0 {
@ -257,15 +262,21 @@ &cps_ethernet {
&cps_eth0 {
status = "okay";
/* Network PHY */
phy = <&phy8>;
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cps_comphy4 0>;
};
&cps_eth1 {
/* CPS Lane 0 - J5 (Gigabit RJ45) */
status = "okay";
/* Network PHY */
phy = <&ge_phy>;
phy-mode = "sgmii";
/* Generic PHY, providing serdes lanes */
phys = <&cps_comphy0 1>;
};
&cps_pinctrl {

11
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
View File

@ -241,6 +241,12 @@ uart1: serial@512100 {
};
watchdog: watchdog@600000 {
compatible = "arm,sbsa-gwdt";
reg = <0x610000 0x1000>, <0x600000 0x1000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
};
ap_sdhci0: sdhci@6e0000 {
compatible = "marvell,armada-ap806-sdhci";
reg = <0x6e0000 0x300>;
@ -263,6 +269,11 @@ ap_clk: clock {
ap_pinctrl: pinctrl {
compatible = "marvell,ap806-pinctrl";
uart0_pins: uart0-pins {
marvell,pins = "mpp11", "mpp19";
marvell,function = "uart0";
};
};
ap_gpio: gpio@1040 {

59
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
View File

@ -74,9 +74,10 @@ cpm_eth0: eth0 {
<ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared";
"tx-cpu3", "rx-shared", "link";
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
@ -87,9 +88,10 @@ cpm_eth1: eth1 {
<ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared";
"tx-cpu3", "rx-shared", "link";
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
@ -100,15 +102,54 @@ cpm_eth2: eth2 {
<ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared";
"tx-cpu3", "rx-shared", "link";
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
};
};
cpm_comphy: phy@120000 {
compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>;
marvell,system-controller = <&cpm_syscon0>;
#address-cells = <1>;
#size-cells = <0>;
cpm_comphy0: phy@0 {
reg = <0>;
#phy-cells = <1>;
};
cpm_comphy1: phy@1 {
reg = <1>;
#phy-cells = <1>;
};
cpm_comphy2: phy@2 {
reg = <2>;
#phy-cells = <1>;
};
cpm_comphy3: phy@3 {
reg = <3>;
#phy-cells = <1>;
};
cpm_comphy4: phy@4 {
reg = <4>;
#phy-cells = <1>;
};
cpm_comphy5: phy@5 {
reg = <5>;
#phy-cells = <1>;
};
};
cpm_mdio: mdio@12a200 {
#address-cells = <1>;
#size-cells = <0>;
@ -143,7 +184,7 @@ cpm_rtc: rtc@284000 {
cpm_syscon0: system-controller@440000 {
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x1000>;
reg = <0x440000 0x2000>;
cpm_clk: clock {
compatible = "marvell,cp110-clock";
@ -274,12 +315,14 @@ cpm_nand: nand@720000 {
* this controller is only usable on the CPM
* for A7K and on the CPS for A8K.
*/
compatible = "marvell,armada370-nand";
compatible = "marvell,armada-8k-nand",
"marvell,armada370-nand";
reg = <0x720000 0x54>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_clk 1 2>;
marvell,system-controller = <&cpm_syscon0>;
status = "disabled";
};

58
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
View File

@ -74,9 +74,10 @@ cps_eth0: eth0 {
<ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared";
"tx-cpu3", "rx-shared", "link";
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
@ -87,9 +88,10 @@ cps_eth1: eth1 {
<ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared";
"tx-cpu3", "rx-shared", "link";
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
@ -100,15 +102,54 @@ cps_eth2: eth2 {
<ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared";
"tx-cpu3", "rx-shared", "link";
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
};
};
cps_comphy: phy@120000 {
compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>;
marvell,system-controller = <&cps_syscon0>;
#address-cells = <1>;
#size-cells = <0>;
cps_comphy0: phy@0 {
reg = <0>;
#phy-cells = <1>;
};
cps_comphy1: phy@1 {
reg = <1>;
#phy-cells = <1>;
};
cps_comphy2: phy@2 {
reg = <2>;
#phy-cells = <1>;
};
cps_comphy3: phy@3 {
reg = <3>;
#phy-cells = <1>;
};
cps_comphy4: phy@4 {
reg = <4>;
#phy-cells = <1>;
};
cps_comphy5: phy@5 {
reg = <5>;
#phy-cells = <1>;
};
};
cps_mdio: mdio@12a200 {
#address-cells = <1>;
#size-cells = <0>;
@ -143,7 +184,7 @@ cps_rtc: rtc@284000 {
cps_syscon0: system-controller@440000 {
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x1000>;
reg = <0x440000 0x2000>;
cps_clk: clock {
compatible = "marvell,cp110-clock";
@ -275,7 +316,8 @@ cps_nand: nand@720000 {
* this controller is only usable on the CPM
* for A7K and on the CPS for A8K.
*/
compatible = "marvell,armada370-nand";
compatible = "marvell,armada370-nand",
"marvell,armada370-nand";
reg = <0x720000 0x54>;
#address-cells = <1>;
#size-cells = <1>;