A second set of Gemini DTS updates for v4.16:

- Use Open Drain flags properly for emulated I2C
 
 - Add the PCI bus to WBD111 and WBD222
 
 - Enable the TVE and panel on DIR-685; the panel driver and
   bindings have been merged into the DRI subsystem.
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Merge tag 'gemini-dts-update-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into next/dt

Pull "A second set of Gemini DTS updates for v4.16" from Linus Walleij:

- Use Open Drain flags properly for emulated I2C

- Add the PCI bus to WBD111 and WBD222

- Enable the TVE and panel on DIR-685; the panel driver and
  bindings have been merged into the DRI subsystem.

* tag 'gemini-dts-update-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
  ARM: dts: Add TVE/TVC and ILI9322 panel to DIR-685
  ARM: dts: Add PCI to WBD111 and WBD222
  ARM: dts: Flags D-Link DIR-685 I2C bus gpios
This commit is contained in:
Arnd Bergmann 2018-01-04 17:55:54 +01:00
commit b304c1c57f
3 changed files with 108 additions and 3 deletions

View File

@ -45,6 +45,47 @@ button-eject {
};
};
vdisp: regulator {
compatible = "regulator-fixed";
regulator-name = "display-power";
regulator-min-microvolt = <3600000>;
regulator-max-microvolt = <3600000>;
/* Collides with LCD E */
gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
spi {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
/* Collides with IDE pins, that's cool (we do not use them) */
gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>;
gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>;
gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>;
/* Collides with pflash CE1, not so cool */
cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
panel: display@0 {
compatible = "dlink,dir-685-panel", "ilitek,ili9322";
reg = <0>;
/* 50 ns min period = 20 MHz */
spi-max-frequency = <20000000>;
spi-cpol; /* Clock active low */
vcc-supply = <&vdisp>;
iovcc-supply = <&vdisp>;
vci-supply = <&vdisp>;
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
};
leds {
compatible = "gpio-leds";
led-wps {
@ -99,8 +140,8 @@ gpio-fan {
gpio-i2c {
compatible = "i2c-gpio";
/* Collides with ICE */
gpios = <&gpio0 5 0>, /* SDA */
<&gpio0 6 0>; /* SCL */
sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
@ -115,7 +156,16 @@ touchkeys@26 {
soc {
flash@30000000 {
status = "okay";
/*
* Flash access is by default disabled, because it
* collides with the Chip Enable signal for the display
* panel, that reuse the parallel flash Chip Select 1
* (CS1). Enabling flash makes graphics stop working.
*
* We might be able to hack around this by letting
* GPIO poke around in the flash controller registers.
*/
/* status = "okay"; */
/* 32MB of flash */
reg = <0x30000000 0x02000000>;
@ -242,5 +292,16 @@ pci@50000000 {
ata@63000000 {
status = "okay";
};
display-controller@6a000000 {
status = "okay";
port@0 {
reg = <0>;
display_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
};

View File

@ -138,5 +138,27 @@ gpio0: gpio@4d000000 {
pinctrl-names = "default";
pinctrl-0 = <&gpio0_default_pins>;
};
pci@50000000 {
status = "okay";
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
<0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
<0x4800 0 0 2 &pci_intc 1>,
<0x4800 0 0 3 &pci_intc 2>,
<0x4800 0 0 4 &pci_intc 3>,
<0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
<0x5000 0 0 2 &pci_intc 2>,
<0x5000 0 0 3 &pci_intc 3>,
<0x5000 0 0 4 &pci_intc 0>,
<0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
<0x5800 0 0 2 &pci_intc 3>,
<0x5800 0 0 3 &pci_intc 0>,
<0x5800 0 0 4 &pci_intc 1>,
<0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
<0x6000 0 0 2 &pci_intc 0>,
<0x6000 0 0 3 &pci_intc 1>,
<0x6000 0 0 4 &pci_intc 2>;
};
};
};

View File

@ -143,5 +143,27 @@ gpio0: gpio@4d000000 {
pinctrl-names = "default";
pinctrl-0 = <&gpio0_default_pins>;
};
pci@50000000 {
status = "okay";
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
<0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
<0x4800 0 0 2 &pci_intc 1>,
<0x4800 0 0 3 &pci_intc 2>,
<0x4800 0 0 4 &pci_intc 3>,
<0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
<0x5000 0 0 2 &pci_intc 2>,
<0x5000 0 0 3 &pci_intc 3>,
<0x5000 0 0 4 &pci_intc 0>,
<0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
<0x5800 0 0 2 &pci_intc 3>,
<0x5800 0 0 3 &pci_intc 0>,
<0x5800 0 0 4 &pci_intc 1>,
<0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
<0x6000 0 0 2 &pci_intc 0>,
<0x6000 0 0 3 &pci_intc 1>,
<0x6000 0 0 4 &pci_intc 2>;
};
};
};