mirror of https://gitee.com/openkylin/linux.git
CLK: Pistachio: Register core clocks
Register the clocks generated by the core clock controller. This includes the 7 PLLs and clocks for the CPU, RPU co-processor, audio, WiFi, bluetooth, and several other peripherals. The MIPS and PERIPH_SYS clocks must remain enabled at all times. Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Cc: James Hartley <james.hartley@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Patchwork: https://patchwork.linux-mips.org/patch/9317/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Andrew Bresticker
Ralf Baechle
parent
43049b0c83
commit
b35d7c3341
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@ -1,2 +1,3 @@
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obj-y += clk.o
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obj-y += clk.o
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obj-y += clk-pll.o
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obj-y += clk-pll.o
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obj-y += clk-pistachio.o
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@ -0,0 +1,199 @@
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/*
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* Pistachio SoC clock controllers
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*
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* Copyright (C) 2014 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#include <linux/clk-provider.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <dt-bindings/clock/pistachio-clk.h>
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#include "clk.h"
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static struct pistachio_gate pistachio_gates[] __initdata = {
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GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),
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GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1),
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GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),
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GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),
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GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),
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GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5),
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GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),
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GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),
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GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8),
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GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104, 9),
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GATE(CLK_RPU_CORE, "rpu_core", "rpu_core_div", 0x104, 10),
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GATE(CLK_WIFI_ADC, "wifi_adc", "wifi_div8_mux", 0x104, 11),
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GATE(CLK_WIFI_DAC, "wifi_dac", "wifi_div4_mux", 0x104, 12),
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GATE(CLK_USB_PHY, "usb_phy", "usb_phy_div", 0x104, 13),
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GATE(CLK_ENET_IN, "enet_in", "enet_clk_in_gate", 0x104, 14),
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GATE(CLK_ENET, "enet", "enet_div", 0x104, 15),
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GATE(CLK_UART0, "uart0", "uart0_div", 0x104, 16),
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GATE(CLK_UART1, "uart1", "uart1_div", 0x104, 17),
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GATE(CLK_PERIPH_SYS, "periph_sys", "sys_internal_div", 0x104, 18),
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GATE(CLK_SPI0, "spi0", "spi0_div", 0x104, 19),
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GATE(CLK_SPI1, "spi1", "spi1_div", 0x104, 20),
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GATE(CLK_EVENT_TIMER, "event_timer", "event_timer_div", 0x104, 21),
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GATE(CLK_AUX_ADC_INTERNAL, "aux_adc_internal", "sys_internal_div",
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0x104, 22),
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GATE(CLK_AUX_ADC, "aux_adc", "aux_adc_div", 0x104, 23),
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GATE(CLK_SD_HOST, "sd_host", "sd_host_div", 0x104, 24),
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GATE(CLK_BT, "bt", "bt_div", 0x104, 25),
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GATE(CLK_BT_DIV4, "bt_div4", "bt_div4_div", 0x104, 26),
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GATE(CLK_BT_DIV8, "bt_div8", "bt_div8_div", 0x104, 27),
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GATE(CLK_BT_1MHZ, "bt_1mhz", "bt_1mhz_div", 0x104, 28),
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};
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static struct pistachio_fixed_factor pistachio_ffs[] __initdata = {
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FIXED_FACTOR(CLK_WIFI_DIV4, "wifi_div4", "wifi_pll", 4),
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FIXED_FACTOR(CLK_WIFI_DIV8, "wifi_div8", "wifi_pll", 8),
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};
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static struct pistachio_div pistachio_divs[] __initdata = {
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DIV(CLK_MIPS_INTERNAL_DIV, "mips_internal_div", "mips_pll_mux",
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0x204, 2),
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DIV(CLK_MIPS_DIV, "mips_div", "mips_internal_div", 0x208, 8),
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DIV_F(CLK_AUDIO_DIV, "audio_div", "audio_mux",
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0x20c, 8, CLK_DIVIDER_ROUND_CLOSEST),
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DIV_F(CLK_I2S_DIV, "i2s_div", "audio_pll_mux",
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0x210, 8, CLK_DIVIDER_ROUND_CLOSEST),
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DIV_F(CLK_SPDIF_DIV, "spdif_div", "audio_pll_mux",
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0x214, 8, CLK_DIVIDER_ROUND_CLOSEST),
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DIV_F(CLK_AUDIO_DAC_DIV, "audio_dac_div", "audio_pll_mux",
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0x218, 8, CLK_DIVIDER_ROUND_CLOSEST),
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DIV(CLK_RPU_V_DIV, "rpu_v_div", "rpu_v_pll_mux", 0x21c, 2),
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DIV(CLK_RPU_L_DIV, "rpu_l_div", "rpu_l_mux", 0x220, 2),
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DIV(CLK_RPU_SLEEP_DIV, "rpu_sleep_div", "xtal", 0x224, 10),
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DIV(CLK_RPU_CORE_DIV, "rpu_core_div", "rpu_core_mux", 0x228, 3),
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DIV(CLK_USB_PHY_DIV, "usb_phy_div", "sys_internal_div", 0x22c, 6),
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DIV(CLK_ENET_DIV, "enet_div", "enet_mux", 0x230, 6),
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DIV_F(CLK_UART0_INTERNAL_DIV, "uart0_internal_div", "sys_pll_mux",
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0x234, 3, CLK_DIVIDER_ROUND_CLOSEST),
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DIV_F(CLK_UART0_DIV, "uart0_div", "uart0_internal_div", 0x238, 10,
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CLK_DIVIDER_ROUND_CLOSEST),
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DIV_F(CLK_UART1_INTERNAL_DIV, "uart1_internal_div", "sys_pll_mux",
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0x23c, 3, CLK_DIVIDER_ROUND_CLOSEST),
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DIV_F(CLK_UART1_DIV, "uart1_div", "uart1_internal_div", 0x240, 10,
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CLK_DIVIDER_ROUND_CLOSEST),
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DIV(CLK_SYS_INTERNAL_DIV, "sys_internal_div", "sys_pll_mux", 0x244, 3),
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DIV(CLK_SPI0_INTERNAL_DIV, "spi0_internal_div", "sys_pll_mux",
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0x248, 3),
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DIV(CLK_SPI0_DIV, "spi0_div", "spi0_internal_div", 0x24c, 7),
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DIV(CLK_SPI1_INTERNAL_DIV, "spi1_internal_div", "sys_pll_mux",
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0x250, 3),
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DIV(CLK_SPI1_DIV, "spi1_div", "spi1_internal_div", 0x254, 7),
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DIV(CLK_EVENT_TIMER_INTERNAL_DIV, "event_timer_internal_div",
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"event_timer_mux", 0x258, 3),
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DIV(CLK_EVENT_TIMER_DIV, "event_timer_div", "event_timer_internal_div",
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0x25c, 12),
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DIV(CLK_AUX_ADC_INTERNAL_DIV, "aux_adc_internal_div",
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"aux_adc_internal", 0x260, 3),
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DIV(CLK_AUX_ADC_DIV, "aux_adc_div", "aux_adc_internal_div", 0x264, 10),
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DIV(CLK_SD_HOST_DIV, "sd_host_div", "sd_host_mux", 0x268, 6),
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DIV(CLK_BT_DIV, "bt_div", "bt_pll_mux", 0x26c, 6),
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DIV(CLK_BT_DIV4_DIV, "bt_div4_div", "bt_pll_mux", 0x270, 6),
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DIV(CLK_BT_DIV8_DIV, "bt_div8_div", "bt_pll_mux", 0x274, 6),
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DIV(CLK_BT_1MHZ_INTERNAL_DIV, "bt_1mhz_internal_div", "bt_pll_mux",
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0x278, 3),
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DIV(CLK_BT_1MHZ_DIV, "bt_1mhz_div", "bt_1mhz_internal_div", 0x27c, 10),
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};
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PNAME(mux_xtal_audio_refclk) = { "xtal", "audio_clk_in_gate" };
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PNAME(mux_xtal_mips) = { "xtal", "mips_pll" };
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PNAME(mux_xtal_audio) = { "xtal", "audio_pll", "audio_in" };
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PNAME(mux_audio_debug) = { "audio_pll_mux", "debug_mux" };
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PNAME(mux_xtal_rpu_v) = { "xtal", "rpu_v_pll" };
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PNAME(mux_xtal_rpu_l) = { "xtal", "rpu_l_pll" };
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PNAME(mux_rpu_l_mips) = { "rpu_l_pll_mux", "mips_pll_mux" };
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PNAME(mux_xtal_wifi) = { "xtal", "wifi_pll" };
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PNAME(mux_xtal_wifi_div4) = { "xtal", "wifi_div4" };
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PNAME(mux_xtal_wifi_div8) = { "xtal", "wifi_div8" };
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PNAME(mux_wifi_div4_rpu_l) = { "wifi_pll_gate", "wifi_div4_mux",
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"rpu_l_pll_mux" };
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PNAME(mux_xtal_sys) = { "xtal", "sys_pll" };
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PNAME(mux_sys_enet) = { "sys_internal_div", "enet_in" };
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PNAME(mux_audio_sys) = { "audio_pll_mux", "sys_internal_div" };
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PNAME(mux_sys_bt) = { "sys_internal_div", "bt_pll_mux" };
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PNAME(mux_xtal_bt) = { "xtal", "bt_pll" };
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static struct pistachio_mux pistachio_muxes[] __initdata = {
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MUX(CLK_AUDIO_REF_MUX, "audio_refclk_mux", mux_xtal_audio_refclk,
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0x200, 0),
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MUX(CLK_MIPS_PLL_MUX, "mips_pll_mux", mux_xtal_mips, 0x200, 1),
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MUX(CLK_AUDIO_PLL_MUX, "audio_pll_mux", mux_xtal_audio, 0x200, 2),
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MUX(CLK_AUDIO_MUX, "audio_mux", mux_audio_debug, 0x200, 4),
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MUX(CLK_RPU_V_PLL_MUX, "rpu_v_pll_mux", mux_xtal_rpu_v, 0x200, 5),
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MUX(CLK_RPU_L_PLL_MUX, "rpu_l_pll_mux", mux_xtal_rpu_l, 0x200, 6),
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MUX(CLK_RPU_L_MUX, "rpu_l_mux", mux_rpu_l_mips, 0x200, 7),
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MUX(CLK_WIFI_PLL_MUX, "wifi_pll_mux", mux_xtal_wifi, 0x200, 8),
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MUX(CLK_WIFI_DIV4_MUX, "wifi_div4_mux", mux_xtal_wifi_div4, 0x200, 9),
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MUX(CLK_WIFI_DIV8_MUX, "wifi_div8_mux", mux_xtal_wifi_div8, 0x200, 10),
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MUX(CLK_RPU_CORE_MUX, "rpu_core_mux", mux_wifi_div4_rpu_l, 0x200, 11),
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MUX(CLK_SYS_PLL_MUX, "sys_pll_mux", mux_xtal_sys, 0x200, 13),
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MUX(CLK_ENET_MUX, "enet_mux", mux_sys_enet, 0x200, 14),
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MUX(CLK_EVENT_TIMER_MUX, "event_timer_mux", mux_audio_sys, 0x200, 15),
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MUX(CLK_SD_HOST_MUX, "sd_host_mux", mux_sys_bt, 0x200, 16),
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MUX(CLK_BT_PLL_MUX, "bt_pll_mux", mux_xtal_bt, 0x200, 17),
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};
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static struct pistachio_pll pistachio_plls[] __initdata = {
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PLL_FIXED(CLK_MIPS_PLL, "mips_pll", "xtal", PLL_GF40LP_LAINT, 0x0),
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PLL_FIXED(CLK_AUDIO_PLL, "audio_pll", "audio_refclk_mux",
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PLL_GF40LP_FRAC, 0xc),
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PLL_FIXED(CLK_RPU_V_PLL, "rpu_v_pll", "xtal", PLL_GF40LP_LAINT, 0x20),
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PLL_FIXED(CLK_RPU_L_PLL, "rpu_l_pll", "xtal", PLL_GF40LP_LAINT, 0x2c),
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PLL_FIXED(CLK_SYS_PLL, "sys_pll", "xtal", PLL_GF40LP_FRAC, 0x38),
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PLL_FIXED(CLK_WIFI_PLL, "wifi_pll", "xtal", PLL_GF40LP_FRAC, 0x4c),
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PLL_FIXED(CLK_BT_PLL, "bt_pll", "xtal", PLL_GF40LP_LAINT, 0x60),
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};
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PNAME(mux_debug) = { "mips_pll_mux", "rpu_v_pll_mux",
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"rpu_l_pll_mux", "sys_pll_mux",
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"wifi_pll_mux", "bt_pll_mux" };
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static u32 mux_debug_idx[] = { 0x0, 0x1, 0x2, 0x4, 0x8, 0x10 };
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static unsigned int pistachio_critical_clks[] __initdata = {
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CLK_MIPS,
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CLK_PERIPH_SYS,
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};
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static void __init pistachio_clk_init(struct device_node *np)
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{
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struct pistachio_clk_provider *p;
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struct clk *debug_clk;
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p = pistachio_clk_alloc_provider(np, CLK_NR_CLKS);
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if (!p)
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return;
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pistachio_clk_register_pll(p, pistachio_plls,
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ARRAY_SIZE(pistachio_plls));
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pistachio_clk_register_mux(p, pistachio_muxes,
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ARRAY_SIZE(pistachio_muxes));
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pistachio_clk_register_div(p, pistachio_divs,
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ARRAY_SIZE(pistachio_divs));
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pistachio_clk_register_fixed_factor(p, pistachio_ffs,
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ARRAY_SIZE(pistachio_ffs));
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pistachio_clk_register_gate(p, pistachio_gates,
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ARRAY_SIZE(pistachio_gates));
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debug_clk = clk_register_mux_table(NULL, "debug_mux", mux_debug,
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ARRAY_SIZE(mux_debug),
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CLK_SET_RATE_NO_REPARENT,
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p->base + 0x200, 18, 0x1f, 0,
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mux_debug_idx, NULL);
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p->clk_data.clks[CLK_DEBUG_MUX] = debug_clk;
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pistachio_clk_register_provider(p);
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pistachio_clk_force_enable(p, pistachio_critical_clks,
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ARRAY_SIZE(pistachio_critical_clks));
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}
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CLK_OF_DECLARE(pistachio_clk, "img,pistachio-clk", pistachio_clk_init);
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