mirror of https://gitee.com/openkylin/linux.git
IOMMU Fixes for Linux v5.5-rc2
Including: - Fix kmemleak warning in IOVA code - Fix compile warnings on ARM32/64 in dma-iommu code due to dma_mask type mismatches - Make ISA reserved regions relaxable, so that VFIO can assign devices which have such regions defined - Fix mapping errors resulting in IO page-faults in the VT-d driver - Make sure direct mappings for a domain are created after the default domain is updated - Map ISA reserved regions in the VT-d driver with correct permissions - Remove unneeded check for PSI capability in the IOTLB flush code of the VT-d driver - Lockdep fix iommu_dma_prepare_msi() -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEr9jSbILcajRFYWYyK/BELZcBGuMFAl38rzEACgkQK/BELZcB GuNPChAAzFdZw0GRphdnsrGog7vJICukFshPifLD8NeJXYzqLzRY89LT/sg4gZrZ K3Uibg8+0OmWl21JqAzDzXeHYUwDV0Xe/ygjeOdqFn3LY8zCo6UcY4OLCZ1az/XU om/yjTBgZjgBcUAxkzRJSdditQ2p7ItEa4dXnlpeCV07vQEmS/5x8JkNsea7CG2h bvBLYW5DpJ1LsJo1WjONHw0DvRkExQsXZaA3zj/6BzfQIXUnkF1Imkgr9gTbXXOl nGHHRLVtsFqv0U5JWz6fZh4/UgvInq45gZIkvvxQWAM/Kn9wxe2RKDwpQJ1wZ8wc S5fwSPa5g5k2X73BbEHx7AFYESpgCRFOeG74i9b7/DlzsbM+aTGPZ1/4kLt9fl+u +AOUV3l9/rqrrmeUEBF7F3kFC9/OL0KIT17xdJfQG1x3RBm9OHy1q0GQH4q8ZbWM aoWg3Ryc4uO/4Majm/kIjADKR0512LvplXsRXhWpud37szhL6vMJDxBb1zKZJgQ1 j/PFUWgolCvmSG1Q048I9pljrsqfE9pgQhmITQ9VAny6eAaZgT7Y21MbBTyQksem /O08TWGAFddH4U9pGnQ1ST/q5hcVvnUgzy12A3MOuOYh5tWfAbeZparjQsu7bFhp uaJudGyXg9Xgrg82XQ2x/Nk710wLRAGG4VKnUz+mBDEzOOmcems= =VWME -----END PGP SIGNATURE----- Merge tag 'iommu-fixes-v5.5-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull iommu fixes from Joerg Roedel: - Fix kmemleak warning in IOVA code - Fix compile warnings on ARM32/64 in dma-iommu code due to dma_mask type mismatches - Make ISA reserved regions relaxable, so that VFIO can assign devices which have such regions defined - Fix mapping errors resulting in IO page-faults in the VT-d driver - Make sure direct mappings for a domain are created after the default domain is updated - Map ISA reserved regions in the VT-d driver with correct permissions - Remove unneeded check for PSI capability in the IOTLB flush code of the VT-d driver - Lockdep fix iommu_dma_prepare_msi() * tag 'iommu-fixes-v5.5-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: iommu/dma: Relax locking in iommu_dma_prepare_msi() iommu/vt-d: Remove incorrect PSI capability check iommu/vt-d: Allocate reserved region for ISA with correct permission iommu: set group default domain before creating direct mappings iommu/vt-d: Fix dmar pte read access not set error iommu/vt-d: Set ISA bridge reserved region as relaxable iommu/dma: Rationalise types for DMA masks iommu/iova: Init the struct iova to fix the possible memleak
This commit is contained in:
Linus Torvalds
commit
b371ddb94f
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@ -19,6 +19,7 @@
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#include <linux/iova.h>
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#include <linux/irq.h>
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#include <linux/mm.h>
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#include <linux/mutex.h>
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#include <linux/pci.h>
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#include <linux/scatterlist.h>
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#include <linux/vmalloc.h>
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@ -44,7 +45,6 @@ struct iommu_dma_cookie {
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dma_addr_t msi_iova;
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};
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struct list_head msi_page_list;
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spinlock_t msi_lock;
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/* Domain for flush queue callback; NULL if flush queue not in use */
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struct iommu_domain *fq_domain;
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@ -63,7 +63,6 @@ static struct iommu_dma_cookie *cookie_alloc(enum iommu_dma_cookie_type type)
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cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
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if (cookie) {
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spin_lock_init(&cookie->msi_lock);
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INIT_LIST_HEAD(&cookie->msi_page_list);
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cookie->type = type;
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}
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@ -399,7 +398,7 @@ static int dma_info_to_prot(enum dma_data_direction dir, bool coherent,
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}
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static dma_addr_t iommu_dma_alloc_iova(struct iommu_domain *domain,
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size_t size, dma_addr_t dma_limit, struct device *dev)
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size_t size, u64 dma_limit, struct device *dev)
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{
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struct iommu_dma_cookie *cookie = domain->iova_cookie;
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struct iova_domain *iovad = &cookie->iovad;
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@ -424,7 +423,7 @@ static dma_addr_t iommu_dma_alloc_iova(struct iommu_domain *domain,
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dma_limit = min_not_zero(dma_limit, dev->bus_dma_limit);
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if (domain->geometry.force_aperture)
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dma_limit = min(dma_limit, domain->geometry.aperture_end);
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dma_limit = min(dma_limit, (u64)domain->geometry.aperture_end);
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/* Try to get PCI devices a SAC address */
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if (dma_limit > DMA_BIT_MASK(32) && dev_is_pci(dev))
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@ -477,7 +476,7 @@ static void __iommu_dma_unmap(struct device *dev, dma_addr_t dma_addr,
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}
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static dma_addr_t __iommu_dma_map(struct device *dev, phys_addr_t phys,
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size_t size, int prot, dma_addr_t dma_mask)
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size_t size, int prot, u64 dma_mask)
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{
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struct iommu_domain *domain = iommu_get_dma_domain(dev);
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struct iommu_dma_cookie *cookie = domain->iova_cookie;
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@ -1176,7 +1175,7 @@ static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *dev,
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if (msi_page->phys == msi_addr)
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return msi_page;
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msi_page = kzalloc(sizeof(*msi_page), GFP_ATOMIC);
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msi_page = kzalloc(sizeof(*msi_page), GFP_KERNEL);
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if (!msi_page)
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return NULL;
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@ -1206,7 +1205,7 @@ int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr)
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struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
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struct iommu_dma_cookie *cookie;
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struct iommu_dma_msi_page *msi_page;
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unsigned long flags;
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static DEFINE_MUTEX(msi_prepare_lock); /* see below */
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if (!domain || !domain->iova_cookie) {
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desc->iommu_cookie = NULL;
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@ -1216,13 +1215,13 @@ int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr)
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cookie = domain->iova_cookie;
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/*
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* We disable IRQs to rule out a possible inversion against
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* irq_desc_lock if, say, someone tries to retarget the affinity
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* of an MSI from within an IPI handler.
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* In fact the whole prepare operation should already be serialised by
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* irq_domain_mutex further up the callchain, but that's pretty subtle
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* on its own, so consider this locking as failsafe documentation...
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*/
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spin_lock_irqsave(&cookie->msi_lock, flags);
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mutex_lock(&msi_prepare_lock);
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msi_page = iommu_dma_get_msi_page(dev, msi_addr, domain);
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spin_unlock_irqrestore(&cookie->msi_lock, flags);
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mutex_unlock(&msi_prepare_lock);
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msi_desc_set_iommu_cookie(desc, msi_page);
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@ -5478,9 +5478,6 @@ static int intel_iommu_map(struct iommu_domain *domain,
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int prot = 0;
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int ret;
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if (dmar_domain->flags & DOMAIN_FLAG_LOSE_CHILDREN)
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return -EINVAL;
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if (iommu_prot & IOMMU_READ)
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prot |= DMA_PTE_READ;
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if (iommu_prot & IOMMU_WRITE)
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@ -5523,8 +5520,6 @@ static size_t intel_iommu_unmap(struct iommu_domain *domain,
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/* Cope with horrid API which requires us to unmap more than the
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size argument if it happens to be a large-page mapping. */
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BUG_ON(!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level));
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if (dmar_domain->flags & DOMAIN_FLAG_LOSE_CHILDREN)
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return 0;
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if (size < VTD_PAGE_SIZE << level_to_offset_bits(level))
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size = VTD_PAGE_SIZE << level_to_offset_bits(level);
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@ -5556,9 +5551,6 @@ static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
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int level = 0;
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u64 phys = 0;
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if (dmar_domain->flags & DOMAIN_FLAG_LOSE_CHILDREN)
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return 0;
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pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level);
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if (pte)
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phys = dma_pte_addr(pte);
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@ -5736,8 +5728,8 @@ static void intel_iommu_get_resv_regions(struct device *device,
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struct pci_dev *pdev = to_pci_dev(device);
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if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) {
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reg = iommu_alloc_resv_region(0, 1UL << 24, 0,
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IOMMU_RESV_DIRECT);
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reg = iommu_alloc_resv_region(0, 1UL << 24, prot,
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IOMMU_RESV_DIRECT_RELAXABLE);
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if (reg)
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list_add_tail(®->list, head);
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}
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@ -104,11 +104,7 @@ static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_d
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{
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struct qi_desc desc;
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/*
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* Do PASID granu IOTLB invalidation if page selective capability is
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* not available.
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*/
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if (pages == -1 || !cap_pgsel_inv(svm->iommu->cap)) {
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if (pages == -1) {
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desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
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QI_EIOTLB_DID(sdev->did) |
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QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
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@ -2282,13 +2282,13 @@ request_default_domain_for_dev(struct device *dev, unsigned long type)
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goto out;
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}
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iommu_group_create_direct_mappings(group, dev);
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/* Make the domain the default for this group */
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if (group->default_domain)
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iommu_domain_free(group->default_domain);
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group->default_domain = domain;
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iommu_group_create_direct_mappings(group, dev);
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dev_info(dev, "Using iommu %s mapping\n",
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type == IOMMU_DOMAIN_DMA ? "dma" : "direct");
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@ -233,7 +233,7 @@ static DEFINE_MUTEX(iova_cache_mutex);
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struct iova *alloc_iova_mem(void)
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{
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return kmem_cache_alloc(iova_cache, GFP_ATOMIC);
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return kmem_cache_zalloc(iova_cache, GFP_ATOMIC);
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}
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EXPORT_SYMBOL(alloc_iova_mem);
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