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clk/exynos5250: add sclk_hdmiphy in the list of special clocks 

hdmi driver needs hdmiphy clock which is one of the parent
for hdmi mux clock. This is required while changing the parent
of mux clock.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Rahul Sharma 2013-07-25 10:37:35 +05:30 committed by Mike Turquette
parent 4a45331488
commit b38a5040a6
2 changed files with 3 additions and 2 deletions
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1
Documentation/devicetree/bindings/clock/exynos5250-clock.txt
View File

@ -61,6 +61,7 @@ clock which they consume.
sclk_spi2 156
div_i2s1 157
div_i2s2 158
sclk_hdmiphy 159
[Peripheral Clock Gates]

4
drivers/clk/samsung/clk-exynos5250.c
View File

@ -88,7 +88,7 @@ enum exynos5250_clks {
sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
div_i2s1, div_i2s2,
div_i2s1, div_i2s2, sclk_hdmiphy,
/* gate clocks */
gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
@ -202,7 +202,7 @@ static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initda
/* fixed rate clocks generated inside the soc */
static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),