mirror of https://gitee.com/openkylin/linux.git
arm64: Process management
The patch adds support for thread creation and context switching. The context switching CPU specific code is introduced with the CPU support patch (part of the arch/arm64/mm/proc.S file). AArch64 supports ASID-tagged TLBs and the ASID can be either 8 or 16-bit wide (detectable via the ID_AA64AFR0_EL1 register). Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Catalin Marinas
parent
1d18c47c73
commit
b3901d54dc
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@ -0,0 +1,152 @@
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/*
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* Based on arch/arm/include/asm/mmu_context.h
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*
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* Copyright (C) 1996 Russell King.
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_MMU_CONTEXT_H
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#define __ASM_MMU_CONTEXT_H
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#include <linux/compiler.h>
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#include <linux/sched.h>
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#include <asm/cacheflush.h>
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#include <asm/proc-fns.h>
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#include <asm-generic/mm_hooks.h>
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#include <asm/cputype.h>
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#include <asm/pgtable.h>
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#define MAX_ASID_BITS 16
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extern unsigned int cpu_last_asid;
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void __init_new_context(struct task_struct *tsk, struct mm_struct *mm);
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void __new_context(struct mm_struct *mm);
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/*
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* Set TTBR0 to empty_zero_page. No translations will be possible via TTBR0.
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*/
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static inline void cpu_set_reserved_ttbr0(void)
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{
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unsigned long ttbr = page_to_phys(empty_zero_page);
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asm(
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" msr ttbr0_el1, %0 // set TTBR0\n"
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" isb"
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:
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: "r" (ttbr));
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}
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static inline void switch_new_context(struct mm_struct *mm)
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{
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unsigned long flags;
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__new_context(mm);
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local_irq_save(flags);
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cpu_switch_mm(mm->pgd, mm);
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local_irq_restore(flags);
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}
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static inline void check_and_switch_context(struct mm_struct *mm,
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struct task_struct *tsk)
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{
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/*
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* Required during context switch to avoid speculative page table
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* walking with the wrong TTBR.
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*/
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cpu_set_reserved_ttbr0();
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if (!((mm->context.id ^ cpu_last_asid) >> MAX_ASID_BITS))
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/*
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* The ASID is from the current generation, just switch to the
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* new pgd. This condition is only true for calls from
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* context_switch() and interrupts are already disabled.
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*/
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cpu_switch_mm(mm->pgd, mm);
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else if (irqs_disabled())
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/*
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* Defer the new ASID allocation until after the context
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* switch critical region since __new_context() cannot be
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* called with interrupts disabled.
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*/
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set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
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else
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/*
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* That is a direct call to switch_mm() or activate_mm() with
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* interrupts enabled and a new context.
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*/
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switch_new_context(mm);
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}
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#define init_new_context(tsk,mm) (__init_new_context(tsk,mm),0)
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#define destroy_context(mm) do { } while(0)
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#define finish_arch_post_lock_switch \
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finish_arch_post_lock_switch
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static inline void finish_arch_post_lock_switch(void)
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{
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if (test_and_clear_thread_flag(TIF_SWITCH_MM)) {
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struct mm_struct *mm = current->mm;
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unsigned long flags;
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__new_context(mm);
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local_irq_save(flags);
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cpu_switch_mm(mm->pgd, mm);
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local_irq_restore(flags);
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}
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}
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/*
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* This is called when "tsk" is about to enter lazy TLB mode.
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*
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* mm: describes the currently active mm context
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* tsk: task which is entering lazy tlb
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* cpu: cpu number which is entering lazy tlb
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*
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* tsk->mm will be NULL
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*/
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static inline void
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enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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}
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/*
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* This is the actual mm switch as far as the scheduler
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* is concerned. No registers are touched. We avoid
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* calling the CPU specific function when the mm hasn't
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* actually changed.
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*/
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static inline void
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switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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unsigned int cpu = smp_processor_id();
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#ifdef CONFIG_SMP
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/* check for possible thread migration */
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if (!cpumask_empty(mm_cpumask(next)) &&
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!cpumask_test_cpu(cpu, mm_cpumask(next)))
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__flush_icache_all();
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#endif
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if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next)
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check_and_switch_context(next, tsk);
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}
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#define deactivate_mm(tsk,mm) do { } while (0)
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#define activate_mm(prev,next) switch_mm(prev, next, NULL)
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#endif
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@ -0,0 +1,127 @@
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/*
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* Based on arch/arm/include/asm/thread_info.h
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*
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* Copyright (C) 2002 Russell King.
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_THREAD_INFO_H
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#define __ASM_THREAD_INFO_H
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#ifdef __KERNEL__
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#include <linux/compiler.h>
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#ifndef CONFIG_ARM64_64K_PAGES
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#define THREAD_SIZE_ORDER 1
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#endif
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#define THREAD_SIZE 8192
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#define THREAD_START_SP (THREAD_SIZE - 16)
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#ifndef __ASSEMBLY__
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struct task_struct;
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struct exec_domain;
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#include <asm/types.h>
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typedef unsigned long mm_segment_t;
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/*
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* low level task data that entry.S needs immediate access to.
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* __switch_to() assumes cpu_context follows immediately after cpu_domain.
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*/
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struct thread_info {
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unsigned long flags; /* low level flags */
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mm_segment_t addr_limit; /* address limit */
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struct task_struct *task; /* main task structure */
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struct exec_domain *exec_domain; /* execution domain */
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struct restart_block restart_block;
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int preempt_count; /* 0 => preemptable, <0 => bug */
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int cpu; /* cpu */
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};
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#define INIT_THREAD_INFO(tsk) \
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{ \
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.task = &tsk, \
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.exec_domain = &default_exec_domain, \
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.flags = 0, \
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.preempt_count = INIT_PREEMPT_COUNT, \
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.addr_limit = KERNEL_DS, \
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.restart_block = { \
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.fn = do_no_restart_syscall, \
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}, \
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}
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#define init_thread_info (init_thread_union.thread_info)
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#define init_stack (init_thread_union.stack)
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/*
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* how to get the thread information struct from C
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*/
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static inline struct thread_info *current_thread_info(void) __attribute_const__;
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static inline struct thread_info *current_thread_info(void)
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{
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register unsigned long sp asm ("sp");
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return (struct thread_info *)(sp & ~(THREAD_SIZE - 1));
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}
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#define thread_saved_pc(tsk) \
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((unsigned long)(tsk->thread.cpu_context.pc))
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#define thread_saved_sp(tsk) \
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((unsigned long)(tsk->thread.cpu_context.sp))
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#define thread_saved_fp(tsk) \
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((unsigned long)(tsk->thread.cpu_context.fp))
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#endif
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/*
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* We use bit 30 of the preempt_count to indicate that kernel
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* preemption is occurring. See <asm/hardirq.h>.
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*/
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#define PREEMPT_ACTIVE 0x40000000
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/*
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* thread information flags:
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* TIF_SYSCALL_TRACE - syscall trace active
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* TIF_SIGPENDING - signal pending
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* TIF_NEED_RESCHED - rescheduling necessary
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* TIF_NOTIFY_RESUME - callback before returning to user
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* TIF_USEDFPU - FPU was used by this task this quantum (SMP)
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* TIF_POLLING_NRFLAG - true if poll_idle() is polling TIF_NEED_RESCHED
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*/
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#define TIF_SIGPENDING 0
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#define TIF_NEED_RESCHED 1
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#define TIF_NOTIFY_RESUME 2 /* callback before returning to user */
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#define TIF_SYSCALL_TRACE 8
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#define TIF_POLLING_NRFLAG 16
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#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
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#define TIF_FREEZE 19
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#define TIF_RESTORE_SIGMASK 20
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#define TIF_SINGLESTEP 21
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#define TIF_32BIT 22 /* 32bit process */
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#define TIF_SWITCH_MM 23 /* deferred switch_mm */
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#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
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#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
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#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
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#define _TIF_32BIT (1 << TIF_32BIT)
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#define _TIF_WORK_MASK (_TIF_NEED_RESCHED | _TIF_SIGPENDING | \
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_TIF_NOTIFY_RESUME)
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#endif /* __KERNEL__ */
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#endif /* __ASM_THREAD_INFO_H */
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@ -0,0 +1,408 @@
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/*
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* Based on arch/arm/kernel/process.c
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*
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* Original Copyright (C) 1995 Linus Torvalds
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* Copyright (C) 1996-2000 Russell King - Converted to ARM.
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdarg.h>
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#include <linux/export.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/stddef.h>
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#include <linux/unistd.h>
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#include <linux/user.h>
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#include <linux/delay.h>
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#include <linux/reboot.h>
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#include <linux/interrupt.h>
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#include <linux/kallsyms.h>
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#include <linux/init.h>
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#include <linux/cpu.h>
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#include <linux/elfcore.h>
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#include <linux/pm.h>
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#include <linux/tick.h>
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#include <linux/utsname.h>
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#include <linux/uaccess.h>
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#include <linux/random.h>
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#include <linux/hw_breakpoint.h>
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#include <linux/personality.h>
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#include <linux/notifier.h>
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#include <asm/compat.h>
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#include <asm/cacheflush.h>
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#include <asm/processor.h>
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#include <asm/stacktrace.h>
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#include <asm/fpsimd.h>
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static void setup_restart(void)
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{
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/*
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* Tell the mm system that we are going to reboot -
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* we may need it to insert some 1:1 mappings so that
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* soft boot works.
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*/
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setup_mm_for_reboot();
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/* Clean and invalidate caches */
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flush_cache_all();
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/* Turn D-cache off */
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cpu_cache_off();
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/* Push out any further dirty data, and ensure cache is empty */
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flush_cache_all();
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}
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void soft_restart(unsigned long addr)
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{
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setup_restart();
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cpu_reset(addr);
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}
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/*
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* Function pointers to optional machine specific functions
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*/
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void (*pm_power_off)(void);
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EXPORT_SYMBOL_GPL(pm_power_off);
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void (*pm_restart)(const char *cmd);
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EXPORT_SYMBOL_GPL(pm_restart);
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/*
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* This is our default idle handler.
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*/
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static void default_idle(void)
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{
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/*
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* This should do all the clock switching and wait for interrupt
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* tricks
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*/
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cpu_do_idle();
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local_irq_enable();
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}
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void (*pm_idle)(void) = default_idle;
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EXPORT_SYMBOL_GPL(pm_idle);
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/*
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* The idle thread, has rather strange semantics for calling pm_idle,
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* but this is what x86 does and we need to do the same, so that
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* things like cpuidle get called in the same way. The only difference
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* is that we always respect 'hlt_counter' to prevent low power idle.
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*/
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void cpu_idle(void)
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{
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local_fiq_enable();
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/* endless idle loop with no priority at all */
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while (1) {
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tick_nohz_idle_enter();
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rcu_idle_enter();
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while (!need_resched()) {
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/*
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* We need to disable interrupts here to ensure
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* we don't miss a wakeup call.
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*/
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local_irq_disable();
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if (!need_resched()) {
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stop_critical_timings();
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pm_idle();
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start_critical_timings();
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/*
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* pm_idle functions should always return
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* with IRQs enabled.
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*/
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WARN_ON(irqs_disabled());
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} else {
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local_irq_enable();
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}
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}
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rcu_idle_exit();
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tick_nohz_idle_exit();
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schedule_preempt_disabled();
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}
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}
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void machine_shutdown(void)
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{
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#ifdef CONFIG_SMP
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smp_send_stop();
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#endif
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}
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void machine_halt(void)
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{
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machine_shutdown();
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while (1);
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}
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void machine_power_off(void)
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{
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machine_shutdown();
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if (pm_power_off)
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pm_power_off();
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}
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void machine_restart(char *cmd)
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{
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machine_shutdown();
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/* Disable interrupts first */
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local_irq_disable();
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local_fiq_disable();
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/* Now call the architecture specific reboot code. */
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if (pm_restart)
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pm_restart(cmd);
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/*
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* Whoops - the architecture was unable to reboot.
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*/
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printk("Reboot failed -- System halted\n");
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while (1);
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}
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void __show_regs(struct pt_regs *regs)
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{
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int i;
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printk("CPU: %d %s (%s %.*s)\n",
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raw_smp_processor_id(), print_tainted(),
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init_utsname()->release,
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(int)strcspn(init_utsname()->version, " "),
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init_utsname()->version);
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print_symbol("PC is at %s\n", instruction_pointer(regs));
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print_symbol("LR is at %s\n", regs->regs[30]);
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printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
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regs->pc, regs->regs[30], regs->pstate);
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printk("sp : %016llx\n", regs->sp);
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for (i = 29; i >= 0; i--) {
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printk("x%-2d: %016llx ", i, regs->regs[i]);
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if (i % 2 == 0)
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printk("\n");
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}
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printk("\n");
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}
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|
||||
void show_regs(struct pt_regs * regs)
|
||||
{
|
||||
printk("\n");
|
||||
printk("Pid: %d, comm: %20s\n", task_pid_nr(current), current->comm);
|
||||
__show_regs(regs);
|
||||
}
|
||||
|
||||
/*
|
||||
* Free current thread data structures etc..
|
||||
*/
|
||||
void exit_thread(void)
|
||||
{
|
||||
}
|
||||
|
||||
void flush_thread(void)
|
||||
{
|
||||
fpsimd_flush_thread();
|
||||
flush_ptrace_hw_breakpoint(current);
|
||||
}
|
||||
|
||||
void release_thread(struct task_struct *dead_task)
|
||||
{
|
||||
}
|
||||
|
||||
int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
|
||||
{
|
||||
fpsimd_save_state(¤t->thread.fpsimd_state);
|
||||
*dst = *src;
|
||||
return 0;
|
||||
}
|
||||
|
||||
asmlinkage void ret_from_fork(void) asm("ret_from_fork");
|
||||
|
||||
int copy_thread(unsigned long clone_flags, unsigned long stack_start,
|
||||
unsigned long stk_sz, struct task_struct *p,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
struct pt_regs *childregs = task_pt_regs(p);
|
||||
unsigned long tls = p->thread.tp_value;
|
||||
|
||||
*childregs = *regs;
|
||||
childregs->regs[0] = 0;
|
||||
|
||||
if (is_compat_thread(task_thread_info(p)))
|
||||
childregs->compat_sp = stack_start;
|
||||
else {
|
||||
/*
|
||||
* Read the current TLS pointer from tpidr_el0 as it may be
|
||||
* out-of-sync with the saved value.
|
||||
*/
|
||||
asm("mrs %0, tpidr_el0" : "=r" (tls));
|
||||
childregs->sp = stack_start;
|
||||
}
|
||||
|
||||
memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
|
||||
p->thread.cpu_context.sp = (unsigned long)childregs;
|
||||
p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
|
||||
|
||||
/* If a TLS pointer was passed to clone, use that for the new thread. */
|
||||
if (clone_flags & CLONE_SETTLS)
|
||||
tls = regs->regs[3];
|
||||
p->thread.tp_value = tls;
|
||||
|
||||
ptrace_hw_copy_thread(p);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tls_thread_switch(struct task_struct *next)
|
||||
{
|
||||
unsigned long tpidr, tpidrro;
|
||||
|
||||
if (!is_compat_task()) {
|
||||
asm("mrs %0, tpidr_el0" : "=r" (tpidr));
|
||||
current->thread.tp_value = tpidr;
|
||||
}
|
||||
|
||||
if (is_compat_thread(task_thread_info(next))) {
|
||||
tpidr = 0;
|
||||
tpidrro = next->thread.tp_value;
|
||||
} else {
|
||||
tpidr = next->thread.tp_value;
|
||||
tpidrro = 0;
|
||||
}
|
||||
|
||||
asm(
|
||||
" msr tpidr_el0, %0\n"
|
||||
" msr tpidrro_el0, %1"
|
||||
: : "r" (tpidr), "r" (tpidrro));
|
||||
}
|
||||
|
||||
/*
|
||||
* Thread switching.
|
||||
*/
|
||||
struct task_struct *__switch_to(struct task_struct *prev,
|
||||
struct task_struct *next)
|
||||
{
|
||||
struct task_struct *last;
|
||||
|
||||
fpsimd_thread_switch(next);
|
||||
tls_thread_switch(next);
|
||||
hw_breakpoint_thread_switch(next);
|
||||
|
||||
/* the actual thread switch */
|
||||
last = cpu_switch_to(prev, next);
|
||||
|
||||
return last;
|
||||
}
|
||||
|
||||
/*
|
||||
* Fill in the task's elfregs structure for a core dump.
|
||||
*/
|
||||
int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs)
|
||||
{
|
||||
elf_core_copy_regs(elfregs, task_pt_regs(t));
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* fill in the fpe structure for a core dump...
|
||||
*/
|
||||
int dump_fpu (struct pt_regs *regs, struct user_fp *fp)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(dump_fpu);
|
||||
|
||||
/*
|
||||
* Shuffle the argument into the correct register before calling the
|
||||
* thread function. x1 is the thread argument, x2 is the pointer to
|
||||
* the thread function, and x3 points to the exit function.
|
||||
*/
|
||||
extern void kernel_thread_helper(void);
|
||||
asm( ".section .text\n"
|
||||
" .align\n"
|
||||
" .type kernel_thread_helper, #function\n"
|
||||
"kernel_thread_helper:\n"
|
||||
" mov x0, x1\n"
|
||||
" mov x30, x3\n"
|
||||
" br x2\n"
|
||||
" .size kernel_thread_helper, . - kernel_thread_helper\n"
|
||||
" .previous");
|
||||
|
||||
#define kernel_thread_exit do_exit
|
||||
|
||||
/*
|
||||
* Create a kernel thread.
|
||||
*/
|
||||
pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
|
||||
{
|
||||
struct pt_regs regs;
|
||||
|
||||
memset(®s, 0, sizeof(regs));
|
||||
|
||||
regs.regs[1] = (unsigned long)arg;
|
||||
regs.regs[2] = (unsigned long)fn;
|
||||
regs.regs[3] = (unsigned long)kernel_thread_exit;
|
||||
regs.pc = (unsigned long)kernel_thread_helper;
|
||||
regs.pstate = PSR_MODE_EL1h;
|
||||
|
||||
return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, ®s, 0, NULL, NULL);
|
||||
}
|
||||
EXPORT_SYMBOL(kernel_thread);
|
||||
|
||||
unsigned long get_wchan(struct task_struct *p)
|
||||
{
|
||||
struct stackframe frame;
|
||||
int count = 0;
|
||||
if (!p || p == current || p->state == TASK_RUNNING)
|
||||
return 0;
|
||||
|
||||
frame.fp = thread_saved_fp(p);
|
||||
frame.sp = thread_saved_sp(p);
|
||||
frame.pc = thread_saved_pc(p);
|
||||
do {
|
||||
int ret = unwind_frame(&frame);
|
||||
if (ret < 0)
|
||||
return 0;
|
||||
if (!in_sched_functions(frame.pc))
|
||||
return frame.pc;
|
||||
} while (count ++ < 16);
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long arch_align_stack(unsigned long sp)
|
||||
{
|
||||
if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
|
||||
sp -= get_random_int() & ~PAGE_MASK;
|
||||
return sp & ~0xf;
|
||||
}
|
||||
|
||||
static unsigned long randomize_base(unsigned long base)
|
||||
{
|
||||
unsigned long range_end = base + (STACK_RND_MASK << PAGE_SHIFT) + 1;
|
||||
return randomize_range(base, range_end, 0) ? : base;
|
||||
}
|
||||
|
||||
unsigned long arch_randomize_brk(struct mm_struct *mm)
|
||||
{
|
||||
return randomize_base(mm->brk);
|
||||
}
|
||||
|
||||
unsigned long randomize_et_dyn(unsigned long base)
|
||||
{
|
||||
return randomize_base(base);
|
||||
}
|
||||
|
|
@ -0,0 +1,159 @@
|
|||
/*
|
||||
* Based on arch/arm/mm/context.c
|
||||
*
|
||||
* Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved.
|
||||
* Copyright (C) 2012 ARM Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/percpu.h>
|
||||
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/tlbflush.h>
|
||||
#include <asm/cachetype.h>
|
||||
|
||||
#define asid_bits(reg) \
|
||||
(((read_cpuid(ID_AA64MMFR0_EL1) & 0xf0) >> 2) + 8)
|
||||
|
||||
#define ASID_FIRST_VERSION (1 << MAX_ASID_BITS)
|
||||
|
||||
static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
|
||||
unsigned int cpu_last_asid = ASID_FIRST_VERSION;
|
||||
|
||||
/*
|
||||
* We fork()ed a process, and we need a new context for the child to run in.
|
||||
*/
|
||||
void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
|
||||
{
|
||||
mm->context.id = 0;
|
||||
raw_spin_lock_init(&mm->context.id_lock);
|
||||
}
|
||||
|
||||
static void flush_context(void)
|
||||
{
|
||||
/* set the reserved TTBR0 before flushing the TLB */
|
||||
cpu_set_reserved_ttbr0();
|
||||
flush_tlb_all();
|
||||
if (icache_is_aivivt())
|
||||
__flush_icache_all();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
|
||||
static void set_mm_context(struct mm_struct *mm, unsigned int asid)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
/*
|
||||
* Locking needed for multi-threaded applications where the same
|
||||
* mm->context.id could be set from different CPUs during the
|
||||
* broadcast. This function is also called via IPI so the
|
||||
* mm->context.id_lock has to be IRQ-safe.
|
||||
*/
|
||||
raw_spin_lock_irqsave(&mm->context.id_lock, flags);
|
||||
if (likely((mm->context.id ^ cpu_last_asid) >> MAX_ASID_BITS)) {
|
||||
/*
|
||||
* Old version of ASID found. Set the new one and reset
|
||||
* mm_cpumask(mm).
|
||||
*/
|
||||
mm->context.id = asid;
|
||||
cpumask_clear(mm_cpumask(mm));
|
||||
}
|
||||
raw_spin_unlock_irqrestore(&mm->context.id_lock, flags);
|
||||
|
||||
/*
|
||||
* Set the mm_cpumask(mm) bit for the current CPU.
|
||||
*/
|
||||
cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
|
||||
}
|
||||
|
||||
/*
|
||||
* Reset the ASID on the current CPU. This function call is broadcast from the
|
||||
* CPU handling the ASID rollover and holding cpu_asid_lock.
|
||||
*/
|
||||
static void reset_context(void *info)
|
||||
{
|
||||
unsigned int asid;
|
||||
unsigned int cpu = smp_processor_id();
|
||||
struct mm_struct *mm = current->active_mm;
|
||||
|
||||
smp_rmb();
|
||||
asid = cpu_last_asid + cpu;
|
||||
|
||||
flush_context();
|
||||
set_mm_context(mm, asid);
|
||||
|
||||
/* set the new ASID */
|
||||
cpu_switch_mm(mm->pgd, mm);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static inline void set_mm_context(struct mm_struct *mm, unsigned int asid)
|
||||
{
|
||||
mm->context.id = asid;
|
||||
cpumask_copy(mm_cpumask(mm), cpumask_of(smp_processor_id()));
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
void __new_context(struct mm_struct *mm)
|
||||
{
|
||||
unsigned int asid;
|
||||
unsigned int bits = asid_bits();
|
||||
|
||||
raw_spin_lock(&cpu_asid_lock);
|
||||
#ifdef CONFIG_SMP
|
||||
/*
|
||||
* Check the ASID again, in case the change was broadcast from another
|
||||
* CPU before we acquired the lock.
|
||||
*/
|
||||
if (!unlikely((mm->context.id ^ cpu_last_asid) >> MAX_ASID_BITS)) {
|
||||
cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
|
||||
raw_spin_unlock(&cpu_asid_lock);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* At this point, it is guaranteed that the current mm (with an old
|
||||
* ASID) isn't active on any other CPU since the ASIDs are changed
|
||||
* simultaneously via IPI.
|
||||
*/
|
||||
asid = ++cpu_last_asid;
|
||||
|
||||
/*
|
||||
* If we've used up all our ASIDs, we need to start a new version and
|
||||
* flush the TLB.
|
||||
*/
|
||||
if (unlikely((asid & ((1 << bits) - 1)) == 0)) {
|
||||
/* increment the ASID version */
|
||||
cpu_last_asid += (1 << MAX_ASID_BITS) - (1 << bits);
|
||||
if (cpu_last_asid == 0)
|
||||
cpu_last_asid = ASID_FIRST_VERSION;
|
||||
asid = cpu_last_asid + smp_processor_id();
|
||||
flush_context();
|
||||
#ifdef CONFIG_SMP
|
||||
smp_wmb();
|
||||
smp_call_function(reset_context, NULL, 1);
|
||||
#endif
|
||||
cpu_last_asid += NR_CPUS - 1;
|
||||
}
|
||||
|
||||
set_mm_context(mm, asid);
|
||||
raw_spin_unlock(&cpu_asid_lock);
|
||||
}
|
||||
Loading…
Reference in New Issue