mirror of https://gitee.com/openkylin/linux.git
dt-bindings: arm: Adds CoreSight CTI hardware definitions
Adds new coresight-cti.yaml file describing the bindings required to define CTI in the device trees. Adds an include file to dt-bindings/arm to define constants describing common signal functionality used in CoreSight and generic usage. Signed-off-by: Mike Leach <mike.leach@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20200320165303.13681-6-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Mike Leach
Greg Kroah-Hartman
parent
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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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# Copyright 2019 Linaro Ltd.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM Coresight Cross Trigger Interface (CTI) device.
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description: |
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The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
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to one or more CoreSight components and/or a CPU, with CTIs interconnected in
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a star topology via the Cross Trigger Matrix (CTM), which is not programmable.
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The ECT components are not part of the trace generation data path and are thus
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not part of the CoreSight graph described in the general CoreSight bindings
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file coresight.txt.
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The CTI component properties define the connections between the individual
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CTI and the components it is directly connected to, consisting of input and
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output hardware trigger signals. CTIs can have a maximum number of input and
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output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The
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number is defined at design time, the maximum of each defined in the DEVID
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register.
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CTIs are interconnected in a star topology via the CTM, using a number of
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programmable channels, usually 4, but again implementation defined and
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described in the DEVID register. The star topology is not required to be
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described in the bindings as the actual connections are software
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programmable.
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In general the connections between CTI and components via the trigger signals
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are implementation defined, except when the CTI is connected to an ARM v8
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architecture core and optional ETM.
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In this case the ARM v8 architecture defines the required signal connections
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between CTI and the CPU core and ETM if present. In the case of a v8
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architecturally connected CTI an additional compatible string is used to
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indicate this feature (arm,coresight-cti-v8-arch).
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When CTI trigger connection information is unavailable then a minimal driver
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binding can be declared with no explicit trigger signals. This will result
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the driver detecting the maximum available triggers and channels from the
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DEVID register and make them all available for use as a single default
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connection. Any user / client application will require additional information
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on the connections between the CTI and other components for correct operation.
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This information might be found by enabling the Integration Test registers in
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the driver (set CONFIG_CORESIGHT_CTI_INTEGRATION_TEST in Kernel
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configuration). These registers may be used to explore the trigger connections
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between CTI and other CoreSight components.
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Certain triggers between CoreSight devices and the CTI have specific types
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and usages. These can be defined along with the signal indexes with the
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constants defined in <dt-bindings/arm/coresight-cti-dt.h>
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For example a CTI connected to a core will usually have a DBGREQ signal. This
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is defined in the binding as type PE_EDBGREQ. These types will appear in an
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optional array alongside the signal indexes. Omitting types will default all
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signals to GEN_IO.
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Note that some hardware trigger signals can be connected to non-CoreSight
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components (e.g. UART etc) depending on hardware implementation.
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maintainers:
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- Mike Leach <mike.leach@linaro.org>
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allOf:
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- $ref: /schemas/arm/primecell.yaml#
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# Need a custom select here or 'arm,primecell' will match on lots of nodes
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select:
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properties:
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compatible:
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contains:
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enum:
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- arm,coresight-cti
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required:
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- compatible
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properties:
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$nodename:
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pattern: "^cti(@[0-9a-f]+)$"
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compatible:
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oneOf:
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- items:
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- const: arm,coresight-cti
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- const: arm,primecell
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- items:
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- const: arm,coresight-cti-v8-arch
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- const: arm,coresight-cti
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- const: arm,primecell
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reg:
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maxItems: 1
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cpu:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Handle to cpu this device is associated with. This must appear in the
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base cti node if compatible string arm,coresight-cti-v8-arch is used,
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or may appear in a trig-conns child node when appropriate.
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arm,cti-ctm-id:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Defines the CTM this CTI is connected to, in large systems with multiple
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separate CTI/CTM nets. Typically multi-socket systems where the CTM is
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propagated between sockets.
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arm,cs-dev-assoc:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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defines a phandle reference to an associated CoreSight trace device.
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When the associated trace device is enabled, then the respective CTI
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will be enabled. Use in a trig-conns node, or in CTI base node when
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compatible string arm,coresight-cti-v8-arch used. If the associated
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device has not been registered then the node name will be stored as
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the connection name for later resolution. If the associated device is
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not a CoreSight device or not registered then the node name will remain
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the connection name and automatic enabling will not occur.
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# size cells and address cells required if trig-conns node present.
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"#size-cells":
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const: 0
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"#address-cells":
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const: 1
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patternProperties:
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'^trig-conns@([0-9]+)$':
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type: object
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description:
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A trigger connections child node which describes the trigger signals
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between this CTI and another hardware device. This device may be a CPU,
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CoreSight device, any other hardware device or simple external IO lines.
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The connection may have both input and output triggers, or only one or the
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other.
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properties:
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reg:
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maxItems: 1
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arm,trig-in-sigs:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 32
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description:
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List of CTI trigger in signal numbers in use by a trig-conns node.
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arm,trig-in-types:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 32
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description:
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List of constants representing the types for the CTI trigger in
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signals. Types in this array match to the corresponding signal in the
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arm,trig-in-sigs array. If the -types array is smaller, or omitted
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completely, then the types will default to GEN_IO.
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arm,trig-out-sigs:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 32
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description:
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List of CTI trigger out signal numbers in use by a trig-conns node.
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arm,trig-out-types:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 32
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description:
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List of constants representing the types for the CTI trigger out
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signals. Types in this array match to the corresponding signal
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in the arm,trig-out-sigs array. If the "-types" array is smaller,
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or omitted completely, then the types will default to GEN_IO.
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arm,trig-filters:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 32
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description:
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List of CTI trigger out signals that will be blocked from becoming
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active, unless filtering is disabled on the driver.
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arm,trig-conn-name:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/string
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description:
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Defines a connection name that will be displayed, if the cpu or
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arm,cs-dev-assoc properties are not being used in this connection.
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Principle use for CTI that are connected to non-CoreSight devices, or
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external IO.
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anyOf:
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- required:
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- arm,trig-in-sigs
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- required:
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- arm,trig-out-sigs
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oneOf:
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- required:
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- arm,trig-conn-name
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- required:
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- cpu
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- required:
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- arm,cs-dev-assoc
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required:
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- reg
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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if:
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properties:
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compatible:
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contains:
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const: arm,coresight-cti-v8-arch
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then:
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required:
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- cpu
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examples:
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# minimum CTI definition. DEVID register used to set number of triggers.
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- |
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cti@20020000 {
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compatible = "arm,coresight-cti", "arm,primecell";
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reg = <0x20020000 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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};
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# v8 architecturally defined CTI - CPU + ETM connections generated by the
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# driver according to the v8 architecture specification.
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- |
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cti@859000 {
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compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
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"arm,primecell";
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reg = <0x859000 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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cpu = <&CPU1>;
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arm,cs-dev-assoc = <&etm1>;
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};
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# Implementation defined CTI - CPU + ETM connections explicitly defined..
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# Shows use of type constants from dt-bindings/arm/coresight-cti-dt.h
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# #size-cells and #address-cells are required if trig-conns@ nodes present.
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- |
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#include <dt-bindings/arm/coresight-cti-dt.h>
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cti@858000 {
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compatible = "arm,coresight-cti", "arm,primecell";
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reg = <0x858000 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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arm,cti-ctm-id = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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trig-conns@0 {
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reg = <0>;
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arm,trig-in-sigs = <4 5 6 7>;
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arm,trig-in-types = <ETM_EXTOUT
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ETM_EXTOUT
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ETM_EXTOUT
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ETM_EXTOUT>;
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arm,trig-out-sigs = <4 5 6 7>;
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arm,trig-out-types = <ETM_EXTIN
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ETM_EXTIN
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ETM_EXTIN
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ETM_EXTIN>;
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arm,cs-dev-assoc = <&etm0>;
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};
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trig-conns@1 {
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reg = <1>;
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cpu = <&CPU0>;
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arm,trig-in-sigs = <0 1>;
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arm,trig-in-types = <PE_DBGTRIGGER
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PE_PMUIRQ>;
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arm,trig-out-sigs=<0 1 2 >;
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arm,trig-out-types = <PE_EDBGREQ
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PE_DBGRESTART
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PE_CTIIRQ>;
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arm,trig-filters = <0>;
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};
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};
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# Implementation defined CTI - non CoreSight component connections.
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- |
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cti@20110000 {
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compatible = "arm,coresight-cti", "arm,primecell";
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reg = <0 0x20110000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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trig-conns@0 {
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reg = <0>;
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arm,trig-in-sigs=<0>;
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arm,trig-in-types=<GEN_INTREQ>;
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arm,trig-out-sigs=<0>;
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arm,trig-out-types=<GEN_HALTREQ>;
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arm,trig-conn-name = "sys_profiler";
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};
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trig-conns@1 {
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reg = <1>;
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arm,trig-out-sigs=<2 3>;
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arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
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arm,trig-conn-name = "watchdog";
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};
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trig-conns@2 {
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reg = <2>;
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arm,trig-in-sigs=<1 6>;
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arm,trig-in-types=<GEN_HALTREQ GEN_RESTARTREQ>;
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arm,trig-conn-name = "g_counter";
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};
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};
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...
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@ -45,6 +45,10 @@ its hardware characteristcs.
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- Coresight Address Translation Unit (CATU)
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"arm,coresight-catu", "arm,primecell";
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- Coresight Cross Trigger Interface (CTI):
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"arm,coresight-cti", "arm,primecell";
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See coresight-cti.yaml for full CTI definitions.
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* reg: physical base address and length of the register
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set(s) of the component.
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@ -72,6 +76,9 @@ its hardware characteristcs.
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* reg-names: the only acceptable values are "stm-base" and
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"stm-stimulus-base", each corresponding to the areas defined in "reg".
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* Required properties for Coresight Cross Trigger Interface (CTI)
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See coresight-cti.yaml for full CTI definitions.
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* Required properties for devices that don't show up on the AMBA bus, such as
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non-configurable replicators and non-configurable funnels:
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@ -1679,9 +1679,11 @@ R: Suzuki K Poulose <suzuki.poulose@arm.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: drivers/hwtracing/coresight/*
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F: include/dt-bindings/arm/coresight-cti-dt.h
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F: Documentation/trace/coresight/*
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F: Documentation/devicetree/bindings/arm/coresight.txt
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F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
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F: Documentation/devicetree/bindings/arm/coresight-cti.yaml
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F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
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F: tools/perf/arch/arm/util/pmu.c
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F: tools/perf/arch/arm/util/auxtrace.c
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@ -0,0 +1,37 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This header provides constants for the defined trigger signal
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* types on CoreSight CTI.
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*/
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#ifndef _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H
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#define _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H
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#define GEN_IO 0
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#define GEN_INTREQ 1
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#define GEN_INTACK 2
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#define GEN_HALTREQ 3
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#define GEN_RESTARTREQ 4
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#define PE_EDBGREQ 5
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#define PE_DBGRESTART 6
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#define PE_CTIIRQ 7
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#define PE_PMUIRQ 8
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#define PE_DBGTRIGGER 9
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#define ETM_EXTOUT 10
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#define ETM_EXTIN 11
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#define SNK_FULL 12
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#define SNK_ACQCOMP 13
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#define SNK_FLUSHCOMP 14
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#define SNK_FLUSHIN 15
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#define SNK_TRIGIN 16
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#define STM_ASYNCOUT 17
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#define STM_TOUT_SPTE 18
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#define STM_TOUT_SW 19
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#define STM_TOUT_HETE 20
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#define STM_HWEVENT 21
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#define ELA_TSTART 22
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#define ELA_TSTOP 23
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#define ELA_DBGREQ 24
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#define CTI_TRIG_MAX 25
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#endif /*_DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H */
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