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irqchip: GICv3: Binding updates for ITS
Add the documentation for the bindings describing the GICv3 ITS. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-14-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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@ -49,11 +49,29 @@ Optional
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occupied by the redistributors. Required if more than one such
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region is present.
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Sub-nodes:
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GICv3 has one or more Interrupt Translation Services (ITS) that are
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used to route Message Signalled Interrupts (MSI) to the CPUs.
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These nodes must have the following properties:
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- compatible : Should at least contain "arm,gic-v3-its".
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- msi-controller : Boolean property. Identifies the node as an MSI controller
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- reg: Specifies the base physical address and size of the ITS
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registers.
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The main GIC node must contain the appropriate #address-cells,
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#size-cells and ranges properties for the reg property of all ITS
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nodes.
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Examples:
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gic: interrupt-controller@2cf00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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reg = <0x0 0x2f000000 0 0x10000>, // GICD
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<0x0 0x2f100000 0 0x200000>, // GICR
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@ -61,11 +79,20 @@ Examples:
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<0x0 0x2c010000 0 0x2000>, // GICH
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<0x0 0x2c020000 0 0x2000>; // GICV
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interrupts = <1 9 4>;
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gic-its@2c200000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0x2c200000 0 0x200000>;
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};
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};
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gic: interrupt-controller@2c010000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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redistributor-stride = <0x0 0x40000>; // 256kB stride
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#redistributor-regions = <2>;
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@ -76,4 +103,16 @@ Examples:
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<0x0 0x2c060000 0 0x2000>, // GICH
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<0x0 0x2c080000 0 0x2000>; // GICV
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interrupts = <1 9 4>;
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gic-its@2c200000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0x2c200000 0 0x200000>;
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};
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gic-its@2c400000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0x2c400000 0 0x200000>;
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};
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};
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