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ARC: [dts] Add clk feeding into timers to DTs 

This allows us to introduce timers in DT in next commit

The core clk frequency hack in AXS103 platform is also extended,
where the core clk feeding into timers is updated in-place in FDT.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta 2016-01-01 18:48:40 +05:30
parent 9ba7648cc9
commit b3d6aba8bd
12 changed files with 79 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arc/boot/dts/axc001.dtsi
View File

@ -26,6 +26,12 @@ cpu_card {
ranges = <0x00000000 0xf0000000 0x10000000>;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <750000000>;
};
core_intc: arc700-intc@cpu {
compatible = "snps,arc700-intc";
interrupt-controller;

6
arch/arc/boot/dts/axc003.dtsi
View File

@ -25,6 +25,12 @@ cpu_card {
ranges = <0x00000000 0xf0000000 0x10000000>;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <90000000>;
};
core_intc: archs-intc@cpu {
compatible = "snps,archs-intc";
interrupt-controller;

6
arch/arc/boot/dts/axc003_idu.dtsi
View File

@ -25,6 +25,12 @@ cpu_card {
ranges = <0x00000000 0xf0000000 0x10000000>;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <90000000>;
};
core_intc: archs-intc@cpu {
compatible = "snps,archs-intc";
interrupt-controller;

6
arch/arc/boot/dts/nsim_700.dts
View File

@ -32,6 +32,12 @@ fpga {
/* child and parent address space 1:1 mapped */
ranges;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <80000000>;
};
core_intc: interrupt-controller {
compatible = "snps,arc700-intc";
interrupt-controller;

6
arch/arc/boot/dts/nsim_hs.dts
View File

@ -39,6 +39,12 @@ fpga {
bus addr, parent bus addr, size */
ranges = <0x80000000 0x0 0x80000000 0x80000000>;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <80000000>;
};
core_intc: core-interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;

6
arch/arc/boot/dts/nsim_hs_idu.dts
View File

@ -29,6 +29,12 @@ fpga {
/* child and parent address space 1:1 mapped */
ranges;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <80000000>;
};
core_intc: core-interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;

6
arch/arc/boot/dts/nsimosci.dts
View File

@ -35,6 +35,12 @@ fpga {
/* child and parent address space 1:1 mapped */
ranges;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <20000000>;
};
core_intc: interrupt-controller {
compatible = "snps,arc700-intc";
interrupt-controller;

6
arch/arc/boot/dts/nsimosci_hs.dts
View File

@ -35,6 +35,12 @@ fpga {
/* child and parent address space 1:1 mapped */
ranges;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <20000000>;
};
core_intc: core-interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;

6
arch/arc/boot/dts/nsimosci_hs_idu.dts
View File

@ -33,6 +33,12 @@ fpga {
/* child and parent address space 1:1 mapped */
ranges;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <5000000>;
};
core_intc: core-interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;

6
arch/arc/boot/dts/vdk_axc003.dtsi
View File

@ -25,6 +25,12 @@ cpu_card {
ranges = <0x00000000 0xf0000000 0x10000000>;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
core_intc: archs-intc@cpu {
compatible = "snps,archs-intc";
interrupt-controller;

6
arch/arc/boot/dts/vdk_axc003_idu.dtsi
View File

@ -26,6 +26,12 @@ cpu_card {
ranges = <0x00000000 0xf0000000 0x10000000>;
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
core_intc: archs-intc@cpu {
compatible = "snps,archs-intc";
interrupt-controller;

14
arch/arc/plat-axs10x/axs10x.c
View File

@ -14,7 +14,9 @@
*
*/
#include <linux/of_fdt.h>
#include <linux/of_platform.h>
#include <linux/libfdt.h>
#include <asm/asm-offsets.h>
#include <asm/clk.h>
@ -389,7 +391,12 @@ axs103_set_freq(unsigned int id, unsigned int fd, unsigned int od)
static void __init axs103_early_init(void)
{
u32 freq = arc_get_core_freq(), orig = freq;
int offset = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
const struct fdt_property *prop = fdt_get_property(initial_boot_params,
offset,
"clock-frequency",
NULL);
u32 freq = be32_to_cpu(*(u32*)(prop->data)) / 1000000, orig = freq;
/*
* AXS103 configurations for SMP/QUAD configurations share device tree
@ -438,8 +445,13 @@ static void __init axs103_early_init(void)
}
pr_info("Freq is %dMHz\n", freq);
/* Patching .dtb in-place with new core clock value */
if (freq != orig ) {
arc_set_core_freq(freq * 1000000);
freq = cpu_to_be32(freq * 1000000);
fdt_setprop_inplace(initial_boot_params, offset,
"clock-frequency", &freq, sizeof(freq));
}
/* Memory maps already config in pre-bootloader */