mirror of https://gitee.com/openkylin/linux.git
phy: sun4i: add support for A64 usb phy
There's something unknown in the pmu part that shared with H3. It's renamed as PMU_UNK1 from PMU_UNK_H3. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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@ -50,7 +50,7 @@
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#define REG_PHYCTL_A33 0x10
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#define REG_PHY_UNK_H3 0x20
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#define REG_PMU_UNK_H3 0x10
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#define REG_PMU_UNK1 0x10
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#define PHYCTL_DATA BIT(7)
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@ -98,6 +98,7 @@ enum sun4i_usb_phy_type {
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sun6i_a31_phy,
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sun8i_a33_phy,
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sun8i_h3_phy,
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sun50i_a64_phy,
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};
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struct sun4i_usb_phy_cfg {
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@ -106,6 +107,7 @@ struct sun4i_usb_phy_cfg {
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u32 disc_thresh;
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u8 phyctl_offset;
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bool dedicated_clocks;
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bool enable_pmu_unk1;
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};
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struct sun4i_usb_phy_data {
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@ -183,8 +185,9 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
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mutex_lock(&phy_data->mutex);
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if (phy_data->cfg->type == sun8i_a33_phy) {
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/* A33 needs us to set phyctl to 0 explicitly */
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if (phy_data->cfg->type == sun8i_a33_phy ||
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phy_data->cfg->type == sun50i_a64_phy) {
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/* A33 or A64 needs us to set phyctl to 0 explicitly */
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writel(0, phyctl);
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}
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@ -258,14 +261,16 @@ static int sun4i_usb_phy_init(struct phy *_phy)
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return ret;
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}
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if (data->cfg->enable_pmu_unk1) {
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val = readl(phy->pmu + REG_PMU_UNK1);
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writel(val & ~2, phy->pmu + REG_PMU_UNK1);
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}
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if (data->cfg->type == sun8i_h3_phy) {
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if (phy->index == 0) {
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val = readl(data->base + REG_PHY_UNK_H3);
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writel(val & ~1, data->base + REG_PHY_UNK_H3);
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}
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val = readl(phy->pmu + REG_PMU_UNK_H3);
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writel(val & ~2, phy->pmu + REG_PMU_UNK_H3);
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} else {
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/* Enable USB 45 Ohm resistor calibration */
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if (phy->index == 0)
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@ -737,6 +742,7 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
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.disc_thresh = 3,
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.phyctl_offset = REG_PHYCTL_A10,
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.dedicated_clocks = false,
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.enable_pmu_unk1 = false,
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};
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static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
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@ -745,6 +751,7 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
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.disc_thresh = 2,
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.phyctl_offset = REG_PHYCTL_A10,
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.dedicated_clocks = false,
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.enable_pmu_unk1 = false,
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};
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static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
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@ -753,6 +760,7 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
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.disc_thresh = 3,
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.phyctl_offset = REG_PHYCTL_A10,
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.dedicated_clocks = true,
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.enable_pmu_unk1 = false,
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};
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static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
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@ -761,6 +769,7 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
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.disc_thresh = 2,
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.phyctl_offset = REG_PHYCTL_A10,
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.dedicated_clocks = false,
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.enable_pmu_unk1 = false,
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};
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static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
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@ -769,6 +778,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
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.disc_thresh = 3,
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.phyctl_offset = REG_PHYCTL_A10,
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.dedicated_clocks = true,
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.enable_pmu_unk1 = false,
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};
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static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
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@ -777,6 +787,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
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.disc_thresh = 3,
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.phyctl_offset = REG_PHYCTL_A33,
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.dedicated_clocks = true,
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.enable_pmu_unk1 = false,
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};
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static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
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@ -784,6 +795,16 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
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.type = sun8i_h3_phy,
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.disc_thresh = 3,
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.dedicated_clocks = true,
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.enable_pmu_unk1 = true,
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};
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static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
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.num_phys = 2,
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.type = sun50i_a64_phy,
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.disc_thresh = 3,
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.phyctl_offset = REG_PHYCTL_A33,
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.dedicated_clocks = true,
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.enable_pmu_unk1 = true,
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};
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static const struct of_device_id sun4i_usb_phy_of_match[] = {
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@ -794,6 +815,8 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
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{ .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg },
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{ .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
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{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
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{ .compatible = "allwinner,sun50i-a64-usb-phy",
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.data = &sun50i_a64_cfg},
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{ },
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};
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MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
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