mirror of https://gitee.com/openkylin/linux.git
PCI: Add ACS quirk for all Cavium devices
Cavium devices matching this quirk do not perform peer-to-peer with other functions, allowing masking out these bits as if they were unimplemented in the ACS capability. Signed-off-by: Manish Jaggi <mjaggi@caviumnetworks.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Tirumalesh Chalamarla <tchalamarla@cavium.com>
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@ -3832,6 +3832,19 @@ static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
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#endif
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}
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static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
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{
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/*
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* Cavium devices matching this quirk do not perform peer-to-peer
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* with other functions, allowing masking out these bits as if they
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* were unimplemented in the ACS capability.
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*/
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acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
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PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
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return acs_flags ? 0 : 1;
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}
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/*
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* Many Intel PCH root ports do provide ACS-like features to disable peer
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* transactions and validate bus numbers in requests, but do not provide an
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@ -3984,6 +3997,8 @@ static const struct pci_dev_acs_enabled {
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{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
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{ 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
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{ 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
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/* Cavium ThunderX */
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{ PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
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{ 0 }
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};
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