mirror of https://gitee.com/openkylin/linux.git
powerpc/xive: Fix dump of XIVE interrupt under pseries
The xmon 'dxi' command calls OPAL to query the XIVE configuration of a interrupt. This can only be done on baremetal (PowerNV) and it will crash a pseries machine. Introduce a new XIVE get_irq_config() operation which implements a different query depending on the platform, PowerNV or pseries, and modify xmon to use a top level wrapper. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20190814154754.23682-3-clg@kaod.org
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@ -99,6 +99,8 @@ extern void xive_flush_interrupt(void);
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/* xmon hook */
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extern void xmon_xive_do_dump(int cpu);
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extern int xmon_xive_get_irq_config(u32 irq, u32 *target, u8 *prio,
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u32 *sw_irq);
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/* APIs used by KVM */
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extern u32 xive_native_default_eq_shift(void);
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@ -257,6 +257,13 @@ notrace void xmon_xive_do_dump(int cpu)
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}
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#endif
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}
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int xmon_xive_get_irq_config(u32 irq, u32 *target, u8 *prio,
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u32 *sw_irq)
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{
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return xive_ops->get_irq_config(irq, target, prio, sw_irq);
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}
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#endif /* CONFIG_XMON */
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static unsigned int xive_get_irq(void)
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@ -111,6 +111,20 @@ int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
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}
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EXPORT_SYMBOL_GPL(xive_native_configure_irq);
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static int xive_native_get_irq_config(u32 hw_irq, u32 *target, u8 *prio,
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u32 *sw_irq)
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{
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s64 rc;
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__be64 vp;
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__be32 lirq;
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rc = opal_xive_get_irq_config(hw_irq, &vp, prio, &lirq);
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*target = be64_to_cpu(vp);
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*sw_irq = be32_to_cpu(lirq);
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return rc == 0 ? 0 : -ENXIO;
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}
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/* This can be called multiple time to change a queue configuration */
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int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
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@ -442,6 +456,7 @@ EXPORT_SYMBOL_GPL(xive_native_sync_queue);
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static const struct xive_ops xive_native_ops = {
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.populate_irq_data = xive_native_populate_irq_data,
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.configure_irq = xive_native_configure_irq,
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.get_irq_config = xive_native_get_irq_config,
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.setup_queue = xive_native_setup_queue,
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.cleanup_queue = xive_native_cleanup_queue,
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.match = xive_native_match,
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@ -215,6 +215,38 @@ static long plpar_int_set_source_config(unsigned long flags,
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return 0;
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}
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static long plpar_int_get_source_config(unsigned long flags,
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unsigned long lisn,
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unsigned long *target,
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unsigned long *prio,
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unsigned long *sw_irq)
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{
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unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
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long rc;
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pr_devel("H_INT_GET_SOURCE_CONFIG flags=%lx lisn=%lx\n", flags, lisn);
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do {
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rc = plpar_hcall(H_INT_GET_SOURCE_CONFIG, retbuf, flags, lisn,
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target, prio, sw_irq);
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} while (plpar_busy_delay(rc));
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if (rc) {
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pr_err("H_INT_GET_SOURCE_CONFIG lisn=%ld failed %ld\n",
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lisn, rc);
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return rc;
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}
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*target = retbuf[0];
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*prio = retbuf[1];
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*sw_irq = retbuf[2];
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pr_devel("H_INT_GET_SOURCE_CONFIG target=%lx prio=%lx sw_irq=%lx\n",
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retbuf[0], retbuf[1], retbuf[2]);
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return 0;
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}
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static long plpar_int_get_queue_info(unsigned long flags,
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unsigned long target,
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unsigned long priority,
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@ -398,6 +430,24 @@ static int xive_spapr_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
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return rc == 0 ? 0 : -ENXIO;
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}
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static int xive_spapr_get_irq_config(u32 hw_irq, u32 *target, u8 *prio,
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u32 *sw_irq)
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{
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long rc;
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unsigned long h_target;
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unsigned long h_prio;
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unsigned long h_sw_irq;
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rc = plpar_int_get_source_config(0, hw_irq, &h_target, &h_prio,
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&h_sw_irq);
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*target = h_target;
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*prio = h_prio;
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*sw_irq = h_sw_irq;
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return rc == 0 ? 0 : -ENXIO;
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}
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/* This can be called multiple time to change a queue configuration */
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static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
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__be32 *qpage, u32 order)
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@ -590,6 +640,7 @@ static void xive_spapr_sync_source(u32 hw_irq)
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static const struct xive_ops xive_spapr_ops = {
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.populate_irq_data = xive_spapr_populate_irq_data,
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.configure_irq = xive_spapr_configure_irq,
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.get_irq_config = xive_spapr_get_irq_config,
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.setup_queue = xive_spapr_setup_queue,
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.cleanup_queue = xive_spapr_cleanup_queue,
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.match = xive_spapr_match,
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@ -33,6 +33,8 @@ struct xive_cpu {
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struct xive_ops {
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int (*populate_irq_data)(u32 hw_irq, struct xive_irq_data *data);
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int (*configure_irq)(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
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int (*get_irq_config)(u32 hw_irq, u32 *target, u8 *prio,
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u32 *sw_irq);
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int (*setup_queue)(unsigned int cpu, struct xive_cpu *xc, u8 prio);
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void (*cleanup_queue)(unsigned int cpu, struct xive_cpu *xc, u8 prio);
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void (*setup_cpu)(unsigned int cpu, struct xive_cpu *xc);
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@ -2574,14 +2574,14 @@ static void dump_all_xives(void)
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static void dump_one_xive_irq(u32 num)
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{
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s64 rc;
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__be64 vp;
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int rc;
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u32 target;
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u8 prio;
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__be32 lirq;
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u32 lirq;
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rc = opal_xive_get_irq_config(num, &vp, &prio, &lirq);
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xmon_printf("IRQ 0x%x config: vp=0x%llx prio=%d lirq=0x%x (rc=%lld)\n",
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num, be64_to_cpu(vp), prio, be32_to_cpu(lirq), rc);
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rc = xmon_xive_get_irq_config(num, &target, &prio, &lirq);
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xmon_printf("IRQ 0x%08x : target=0x%x prio=%d lirq=0x%x (rc=%d)\n",
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num, target, prio, lirq, rc);
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}
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static void dump_xives(void)
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