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drm/amd/powerplay: update all printk to pr_* on hwmgr 

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Huang Rui 2016-12-26 15:00:22 +08:00 committed by Alex Deucher
parent 19946cfd37
commit b5c11b8e37
7 changed files with 43 additions and 43 deletions
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26
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
View File

@ -287,7 +287,7 @@ static int cz_init_dynamic_state_adjustment_rule_settings(
kzalloc(table_size, GFP_KERNEL); kzalloc(table_size, GFP_KERNEL);
if (NULL == table_clk_vlt) { if (NULL == table_clk_vlt) {
printk(KERN_ERR "[ powerplay ] Can not allocate memory!\n"); pr_err("Can not allocate memory!\n");
return -ENOMEM; return -ENOMEM;
} }
@ -328,12 +328,12 @@ static int cz_get_system_info_data(struct pp_hwmgr *hwmgr)
&size, &frev, &crev); &size, &frev, &crev);
if (crev != 9) { if (crev != 9) {
printk(KERN_ERR "[ powerplay ] Unsupported IGP table: %d %d\n", frev, crev); pr_err("Unsupported IGP table: %d %d\n", frev, crev);
return -EINVAL; return -EINVAL;
} }
if (info == NULL) { if (info == NULL) {
printk(KERN_ERR "[ powerplay ] Could not retrieve the Integrated System Info Table!\n"); pr_err("Could not retrieve the Integrated System Info Table!\n");
return -EINVAL; return -EINVAL;
} }
@ -360,7 +360,7 @@ static int cz_get_system_info_data(struct pp_hwmgr *hwmgr)
if (cz_hwmgr->sys_info.htc_tmp_lmt <= if (cz_hwmgr->sys_info.htc_tmp_lmt <=
cz_hwmgr->sys_info.htc_hyst_lmt) { cz_hwmgr->sys_info.htc_hyst_lmt) {
printk(KERN_ERR "[ powerplay ] The htcTmpLmt should be larger than htcHystLmt.\n"); pr_err("The htcTmpLmt should be larger than htcHystLmt.\n");
return -EINVAL; return -EINVAL;
} }
@ -722,7 +722,7 @@ static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
clock = hwmgr->display_config.min_core_set_clock; clock = hwmgr->display_config.min_core_set_clock;
if (clock == 0) if (clock == 0)
printk(KERN_INFO "[ powerplay ] min_core_set_clock not set\n"); pr_info("min_core_set_clock not set\n");
if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) { if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
cz_hwmgr->sclk_dpm.hard_min_clk = clock; cz_hwmgr->sclk_dpm.hard_min_clk = clock;
@ -1161,13 +1161,13 @@ static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
result = cz_initialize_dpm_defaults(hwmgr); result = cz_initialize_dpm_defaults(hwmgr);
if (result != 0) { if (result != 0) {
printk(KERN_ERR "[ powerplay ] cz_initialize_dpm_defaults failed\n"); pr_err("cz_initialize_dpm_defaults failed\n");
return result; return result;
} }
result = cz_get_system_info_data(hwmgr); result = cz_get_system_info_data(hwmgr);
if (result != 0) { if (result != 0) {
printk(KERN_ERR "[ powerplay ] cz_get_system_info_data failed\n"); pr_err("cz_get_system_info_data failed\n");
return result; return result;
} }
@ -1176,40 +1176,40 @@ static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
result = phm_construct_table(hwmgr, &cz_setup_asic_master, result = phm_construct_table(hwmgr, &cz_setup_asic_master,
&(hwmgr->setup_asic)); &(hwmgr->setup_asic));
if (result != 0) { if (result != 0) {
printk(KERN_ERR "[ powerplay ] Fail to construct setup ASIC\n"); pr_err("Fail to construct setup ASIC\n");
return result; return result;
} }
result = phm_construct_table(hwmgr, &cz_power_down_asic_master, result = phm_construct_table(hwmgr, &cz_power_down_asic_master,
&(hwmgr->power_down_asic)); &(hwmgr->power_down_asic));
if (result != 0) { if (result != 0) {
printk(KERN_ERR "[ powerplay ] Fail to construct power down ASIC\n"); pr_err("Fail to construct power down ASIC\n");
return result; return result;
} }
result = phm_construct_table(hwmgr, &cz_disable_dpm_master, result = phm_construct_table(hwmgr, &cz_disable_dpm_master,
&(hwmgr->disable_dynamic_state_management)); &(hwmgr->disable_dynamic_state_management));
if (result != 0) { if (result != 0) {
printk(KERN_ERR "[ powerplay ] Fail to disable_dynamic_state\n"); pr_err("Fail to disable_dynamic_state\n");
return result; return result;
} }
result = phm_construct_table(hwmgr, &cz_enable_dpm_master, result = phm_construct_table(hwmgr, &cz_enable_dpm_master,
&(hwmgr->enable_dynamic_state_management)); &(hwmgr->enable_dynamic_state_management));
if (result != 0) { if (result != 0) {
printk(KERN_ERR "[ powerplay ] Fail to enable_dynamic_state\n"); pr_err("Fail to enable_dynamic_state\n");
return result; return result;
} }
result = phm_construct_table(hwmgr, &cz_set_power_state_master, result = phm_construct_table(hwmgr, &cz_set_power_state_master,
&(hwmgr->set_power_state)); &(hwmgr->set_power_state));
if (result != 0) { if (result != 0) {
printk(KERN_ERR "[ powerplay ] Fail to construct set_power_state\n"); pr_err("Fail to construct set_power_state\n");
return result; return result;
} }
hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = CZ_MAX_HARDWARE_POWERLEVELS; hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = CZ_MAX_HARDWARE_POWERLEVELS;
result = phm_construct_table(hwmgr, &cz_phm_enable_clock_power_gatings_master, &(hwmgr->enable_clock_power_gatings)); result = phm_construct_table(hwmgr, &cz_phm_enable_clock_power_gatings_master, &(hwmgr->enable_clock_power_gatings));
if (result != 0) { if (result != 0) {
printk(KERN_ERR "[ powerplay ] Fail to construct enable_clock_power_gatings\n"); pr_err("Fail to construct enable_clock_power_gatings\n");
return result; return result;
} }
return result; return result;

14
drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
View File

@ -35,7 +35,7 @@ static int phm_run_table(struct pp_hwmgr *hwmgr,
phm_table_function *function; phm_table_function *function;
if (rt_table->function_list == NULL) { if (rt_table->function_list == NULL) {
pr_debug("[ powerplay ] this function not implement!\n"); pr_debug("this function not implement!\n");
return 0; return 0;
} }
@ -63,14 +63,14 @@ int phm_dispatch_table(struct pp_hwmgr *hwmgr,
void *temp_storage; void *temp_storage;
if (hwmgr == NULL || rt_table == NULL) { if (hwmgr == NULL || rt_table == NULL) {
printk(KERN_ERR "[ powerplay ] Invalid Parameter!\n"); pr_err("Invalid Parameter!\n");
return -EINVAL; return -EINVAL;
} }
if (0 != rt_table->storage_size) { if (0 != rt_table->storage_size) {
temp_storage = kzalloc(rt_table->storage_size, GFP_KERNEL); temp_storage = kzalloc(rt_table->storage_size, GFP_KERNEL);
if (temp_storage == NULL) { if (temp_storage == NULL) {
printk(KERN_ERR "[ powerplay ] Could not allocate table temporary storage\n"); pr_err("Could not allocate table temporary storage\n");
return -ENOMEM; return -ENOMEM;
} }
} else { } else {
@ -95,7 +95,7 @@ int phm_construct_table(struct pp_hwmgr *hwmgr,
phm_table_function *rtf; phm_table_function *rtf;
if (hwmgr == NULL || master_table == NULL || rt_table == NULL) { if (hwmgr == NULL || master_table == NULL || rt_table == NULL) {
printk(KERN_ERR "[ powerplay ] Invalid Parameter!\n"); pr_err("Invalid Parameter!\n");
return -EINVAL; return -EINVAL;
} }
@ -116,7 +116,7 @@ int phm_construct_table(struct pp_hwmgr *hwmgr,
for (table_item = master_table->master_list; for (table_item = master_table->master_list;
NULL != table_item->tableFunction; table_item++) { NULL != table_item->tableFunction; table_item++) {
if ((rtf - run_time_list) > function_count) { if ((rtf - run_time_list) > function_count) {
printk(KERN_ERR "[ powerplay ] Check function results have changed\n"); pr_err("Check function results have changed\n");
kfree(run_time_list); kfree(run_time_list);
return -EINVAL; return -EINVAL;
} }
@ -128,7 +128,7 @@ int phm_construct_table(struct pp_hwmgr *hwmgr,
} }
if ((rtf - run_time_list) > function_count) { if ((rtf - run_time_list) > function_count) {
printk(KERN_ERR "[ powerplay ] Check function results have changed\n"); pr_err("Check function results have changed\n");
kfree(run_time_list); kfree(run_time_list);
return -EINVAL; return -EINVAL;
} }
@ -144,7 +144,7 @@ int phm_destroy_table(struct pp_hwmgr *hwmgr,
struct phm_runtime_table_header *rt_table) struct phm_runtime_table_header *rt_table)
{ {
if (hwmgr == NULL || rt_table == NULL) { if (hwmgr == NULL || rt_table == NULL) {
printk(KERN_ERR "[ powerplay ] Invalid Parameter\n"); pr_err("Invalid Parameter\n");
return -EINVAL; return -EINVAL;
} }

8
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
View File

@ -198,7 +198,7 @@ int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
uint32_t cur_value; uint32_t cur_value;
if (hwmgr == NULL || hwmgr->device == NULL) { if (hwmgr == NULL || hwmgr->device == NULL) {
printk(KERN_ERR "[ powerplay ] Invalid Hardware Manager!"); pr_err("Invalid Hardware Manager!");
return -EINVAL; return -EINVAL;
} }
@ -228,7 +228,7 @@ void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
uint32_t mask) uint32_t mask)
{ {
if (hwmgr == NULL || hwmgr->device == NULL) { if (hwmgr == NULL || hwmgr->device == NULL) {
printk(KERN_ERR "[ powerplay ] Invalid Hardware Manager!"); pr_err("Invalid Hardware Manager!");
return; return;
} }
@ -550,7 +550,7 @@ int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr
table_clk_vlt = kzalloc(table_size, GFP_KERNEL); table_clk_vlt = kzalloc(table_size, GFP_KERNEL);
if (NULL == table_clk_vlt) { if (NULL == table_clk_vlt) {
printk(KERN_ERR "[ powerplay ] Can not allocate space for vddc_dep_on_dal_pwrl! \n"); pr_err("Can not allocate space for vddc_dep_on_dal_pwrl! \n");
return -ENOMEM; return -ENOMEM;
} else { } else {
table_clk_vlt->count = 4; table_clk_vlt->count = 4;
@ -626,7 +626,7 @@ void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
return; return;
} }
} }
printk(KERN_ERR "DAL requested level can not" pr_err("DAL requested level can not"
" found a available voltage in VDDC DPM Table \n"); " found a available voltage in VDDC DPM Table \n");
} }

6
drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
View File

@ -145,10 +145,10 @@ int atomctrl_initialize_mc_reg_table(
GetIndexIntoMasterTable(DATA, VRAM_Info), &size, &frev, &crev); GetIndexIntoMasterTable(DATA, VRAM_Info), &size, &frev, &crev);
if (module_index >= vram_info->ucNumOfVRAMModule) { if (module_index >= vram_info->ucNumOfVRAMModule) {
printk(KERN_ERR "[ powerplay ] Invalid VramInfo table."); pr_err("Invalid VramInfo table.");
result = -1; result = -1;
} else if (vram_info->sHeader.ucTableFormatRevision < 2) { } else if (vram_info->sHeader.ucTableFormatRevision < 2) {
printk(KERN_ERR "[ powerplay ] Invalid VramInfo table."); pr_err("Invalid VramInfo table.");
result = -1; result = -1;
} }
@ -688,7 +688,7 @@ int atomctrl_calculate_voltage_evv_on_sclk(
fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM7), 1000); fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM7), 1000);
break; break;
default: default:
printk(KERN_ERR "DPM Level not supported\n"); pr_err("DPM Level not supported\n");
fPowerDPMx = Convert_ULONG_ToFraction(1); fPowerDPMx = Convert_ULONG_ToFraction(1);
fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM0), 1000); fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM0), 1000);
} }

4
drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
View File

@ -535,7 +535,7 @@ static int get_pcie_table(
if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count) if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)
pcie_count = (uint32_t)atom_pcie_table->ucNumEntries; pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;
else else
printk(KERN_ERR "[ powerplay ] Number of Pcie Entries exceed the number of SCLK Dpm Levels! \ pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! \
Disregarding the excess entries... \n"); Disregarding the excess entries... \n");
pcie_table->count = pcie_count; pcie_table->count = pcie_count;
@ -577,7 +577,7 @@ static int get_pcie_table(
if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count) if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)
pcie_count = (uint32_t)atom_pcie_table->ucNumEntries; pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;
else else
printk(KERN_ERR "[ powerplay ] Number of Pcie Entries exceed the number of SCLK Dpm Levels! \ pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! \
Disregarding the excess entries... \n"); Disregarding the excess entries... \n");
pcie_table->count = pcie_count; pcie_table->count = pcie_count;

26
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
View File

@ -996,7 +996,7 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
SWRST_COMMAND_1, RESETLC, 0x0); SWRST_COMMAND_1, RESETLC, 0x0);
if (smu7_enable_sclk_mclk_dpm(hwmgr)) { if (smu7_enable_sclk_mclk_dpm(hwmgr)) {
printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!"); pr_err("Failed to enable Sclk DPM and Mclk DPM!");
return -EINVAL; return -EINVAL;
} }
@ -1081,7 +1081,7 @@ static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
switch (sources) { switch (sources) {
default: default:
printk(KERN_ERR "Unknown throttling event sources."); pr_err("Unknown throttling event sources.");
/* fall through */ /* fall through */
case 0: case 0:
protection = false; protection = false;
@ -1501,7 +1501,7 @@ static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
data->vddcgfx_leakage.count++; data->vddcgfx_leakage.count++;
} }
} else { } else {
printk("Error retrieving EVV voltage value!\n"); pr_info("Error retrieving EVV voltage value!\n");
} }
} }
} else { } else {
@ -1529,7 +1529,7 @@ static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
if (vddc >= 2000 || vddc == 0) if (vddc >= 2000 || vddc == 0)
return -EINVAL; return -EINVAL;
} else { } else {
printk(KERN_WARNING "failed to retrieving EVV voltage!\n"); pr_warning("failed to retrieving EVV voltage!\n");
continue; continue;
} }
@ -1569,7 +1569,7 @@ static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr *hwmgr,
} }
if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n"); pr_err("Voltage value looks like a Leakage ID but it's not patched \n");
} }
/** /**
@ -2034,7 +2034,7 @@ static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr *hwmgr,
} }
if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n"); pr_err("Voltage value looks like a Leakage ID but it's not patched \n");
} }
@ -2287,7 +2287,7 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
result = smu7_get_evv_voltages(hwmgr); result = smu7_get_evv_voltages(hwmgr);
if (result) { if (result) {
printk("Get EVV Voltage Failed. Abort Driver loading!\n"); pr_info("Get EVV Voltage Failed. Abort Driver loading!\n");
return -EINVAL; return -EINVAL;
} }
@ -2900,11 +2900,11 @@ static int smu7_get_pp_table_entry_v1(struct pp_hwmgr *hwmgr,
if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
if (dep_mclk_table->entries[0].clk != if (dep_mclk_table->entries[0].clk !=
data->vbios_boot_state.mclk_bootup_value) data->vbios_boot_state.mclk_bootup_value)
printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table " pr_err("Single MCLK entry VDDCI/MCLK dependency table "
"does not match VBIOS boot MCLK level"); "does not match VBIOS boot MCLK level");
if (dep_mclk_table->entries[0].vddci != if (dep_mclk_table->entries[0].vddci !=
data->vbios_boot_state.vddci_bootup_value) data->vbios_boot_state.vddci_bootup_value)
printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table " pr_err("Single VDDCI entry VDDCI/MCLK dependency table "
"does not match VBIOS boot VDDCI level"); "does not match VBIOS boot VDDCI level");
} }
@ -3048,11 +3048,11 @@ static int smu7_get_pp_table_entry_v0(struct pp_hwmgr *hwmgr,
if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
if (dep_mclk_table->entries[0].clk != if (dep_mclk_table->entries[0].clk !=
data->vbios_boot_state.mclk_bootup_value) data->vbios_boot_state.mclk_bootup_value)
printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table " pr_err("Single MCLK entry VDDCI/MCLK dependency table "
"does not match VBIOS boot MCLK level"); "does not match VBIOS boot MCLK level");
if (dep_mclk_table->entries[0].v != if (dep_mclk_table->entries[0].v !=
data->vbios_boot_state.vddci_bootup_value) data->vbios_boot_state.vddci_bootup_value)
printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table " pr_err("Single VDDCI entry VDDCI/MCLK dependency table "
"does not match VBIOS boot VDDCI level"); "does not match VBIOS boot VDDCI level");
} }
@ -3592,9 +3592,9 @@ static int smu7_notify_link_speed_change_after_state_change(
if (acpi_pcie_perf_request(hwmgr->device, request, false)) { if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
if (PP_PCIEGen2 == target_link_speed) if (PP_PCIEGen2 == target_link_speed)
printk("PSPP request to switch to Gen2 from Gen3 Failed!"); pr_info("PSPP request to switch to Gen2 from Gen3 Failed!");
else else
printk("PSPP request to switch to Gen1 from Gen2 Failed!"); pr_info("PSPP request to switch to Gen1 from Gen2 Failed!");
} }
} }

2
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
View File

@ -651,7 +651,7 @@ int smu7_enable_power_containment(struct pp_hwmgr *hwmgr)
POWERCONTAINMENT_FEATURE_PkgPwrLimit; POWERCONTAINMENT_FEATURE_PkgPwrLimit;
if (smu7_set_power_limit(hwmgr, default_limit)) if (smu7_set_power_limit(hwmgr, default_limit))
printk(KERN_ERR "Failed to set Default Power Limit in SMC!"); pr_err("Failed to set Default Power Limit in SMC!");
} }
} }
} }