mirror of https://gitee.com/openkylin/linux.git
x86: add NOPL as a synthetic CPU feature bit
The long noops ("NOPL") are supposed to be detected by family >= 6. Unfortunately, several non-Intel x86 implementations, both hardware and software, don't obey this dictum. Instead, probe for NOPL directly by executing a NOPL instruction and see if we get #UD. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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@ -13,6 +13,7 @@
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#include <asm/mtrr.h>
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#include <asm/mce.h>
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#include <asm/pat.h>
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#include <asm/asm.h>
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#ifdef CONFIG_X86_LOCAL_APIC
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#include <asm/mpspec.h>
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#include <asm/apic.h>
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@ -341,6 +342,35 @@ static void __init early_cpu_detect(void)
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early_get_cap(c);
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}
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/*
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* The NOPL instruction is supposed to exist on all CPUs with
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* family >= 6, unfortunately, that's not true in practice because
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* of early VIA chips and (more importantly) broken virtualizers that
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* are not easy to detect. Hence, probe for it based on first
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* principles.
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*/
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static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
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{
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const u32 nopl_signature = 0x888c53b1; /* Random number */
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u32 has_nopl = nopl_signature;
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clear_cpu_cap(c, X86_FEATURE_NOPL);
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if (c->x86 >= 6) {
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asm volatile("\n"
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"1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
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"2:\n"
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" .section .fixup,\"ax\"\n"
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"3: xor %0,%0\n"
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" jmp 2b\n"
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" .previous\n"
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_ASM_EXTABLE(1b,3b)
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: "+a" (has_nopl));
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if (has_nopl == nopl_signature)
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set_cpu_cap(c, X86_FEATURE_NOPL);
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}
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}
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static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
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{
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u32 tfms, xlvl;
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@ -395,8 +425,8 @@ static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
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}
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init_scattered_cpuid_features(c);
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detect_nopl(c);
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}
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}
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static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
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@ -18,6 +18,7 @@
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#include <asm/mtrr.h>
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#include <asm/mce.h>
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#include <asm/pat.h>
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#include <asm/asm.h>
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#include <asm/numa.h>
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#ifdef CONFIG_X86_LOCAL_APIC
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#include <asm/mpspec.h>
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@ -215,6 +216,39 @@ static void __init early_cpu_support_print(void)
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}
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}
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/*
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* The NOPL instruction is supposed to exist on all CPUs with
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* family >= 6, unfortunately, that's not true in practice because
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* of early VIA chips and (more importantly) broken virtualizers that
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* are not easy to detect. Hence, probe for it based on first
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* principles.
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*
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* Note: no 64-bit chip is known to lack these, but put the code here
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* for consistency with 32 bits, and to make it utterly trivial to
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* diagnose the problem should it ever surface.
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*/
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static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
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{
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const u32 nopl_signature = 0x888c53b1; /* Random number */
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u32 has_nopl = nopl_signature;
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clear_cpu_cap(c, X86_FEATURE_NOPL);
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if (c->x86 >= 6) {
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asm volatile("\n"
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"1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
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"2:\n"
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" .section .fixup,\"ax\"\n"
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"3: xor %0,%0\n"
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" jmp 2b\n"
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" .previous\n"
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_ASM_EXTABLE(1b,3b)
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: "+a" (has_nopl));
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if (has_nopl == nopl_signature)
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set_cpu_cap(c, X86_FEATURE_NOPL);
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}
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}
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static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
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void __init early_cpu_init(void)
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@ -313,6 +347,8 @@ static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
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c->x86_phys_bits = eax & 0xff;
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}
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detect_nopl(c);
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if (c->x86_vendor != X86_VENDOR_UNKNOWN &&
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cpu_devs[c->x86_vendor]->c_early_init)
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cpu_devs[c->x86_vendor]->c_early_init(c);
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@ -39,7 +39,8 @@ const char * const x86_cap_flags[NCAPINTS*32] = {
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NULL, NULL, NULL, NULL,
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"constant_tsc", "up", NULL, "arch_perfmon",
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"pebs", "bts", NULL, NULL,
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"rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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"rep_good", NULL, NULL, NULL,
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"nopl", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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/* Intel-defined (#2) */
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@ -72,14 +72,15 @@
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#define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */
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#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */
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#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
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#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
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#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
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#define X86_FEATURE_SYSCALL32 (3*32+14) /* syscall in ia32 userspace */
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#define X86_FEATURE_SYSENTER32 (3*32+15) /* sysenter in ia32 userspace */
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#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
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#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
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#define X86_FEATURE_SYSCALL32 (3*32+14) /* syscall in ia32 userspace */
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#define X86_FEATURE_SYSENTER32 (3*32+15) /* sysenter in ia32 userspace */
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#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */
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#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
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#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */
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#define X86_FEATURE_11AP (3*32+19) /* Bad local APIC aka 11AP */
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#define X86_FEATURE_11AP (3*32+19) /* Bad local APIC aka 11AP */
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#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */
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/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
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#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
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@ -41,6 +41,12 @@
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# define NEED_3DNOW 0
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#endif
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#if defined(CONFIG_X86_P6_NOP) || defined(CONFIG_X86_64)
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# define NEED_NOPL (1<<(X86_FEATURE_NOPL & 31))
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#else
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# define NEED_NOPL 0
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#endif
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#ifdef CONFIG_X86_64
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#define NEED_PSE 0
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#define NEED_MSR (1<<(X86_FEATURE_MSR & 31))
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@ -67,7 +73,7 @@
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#define REQUIRED_MASK1 (NEED_LM|NEED_3DNOW)
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#define REQUIRED_MASK2 0
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#define REQUIRED_MASK3 0
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#define REQUIRED_MASK3 (NEED_NOPL)
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#define REQUIRED_MASK4 0
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#define REQUIRED_MASK5 0
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#define REQUIRED_MASK6 0
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